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 LINE       12819
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T138,T139,T141
1	1	1	Covered	T48,T49,T50

 LINE       12824
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Not Covered
1	1	1	Covered	T48,T49,T50

 LINE       12825
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T139,T145,T268
1	1	1	Covered	T48,T49,T50

 LINE       12842
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T53,T138,T139
1	1	1	Covered	T48,T49,T50

 LINE       12847
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T49,T53,T54
1	1	0	Covered	T53,T54,T141
1	1	1	Not Covered

 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T54,T139,T144
1	1	1	Covered	T48,T49,T195

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T53,T138,T139
1	1	1	Covered	T48,T49,T50

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Covered	T53,T139,T141
1	1	1	Covered	T48,T49,T50

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T16,T48,T49
1	0	1	Covered	T48,T49,T53
1	1	0	Not Covered
1	1	1	Covered	T48,T49,T50

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T291
1	1	Covered	T16,T48,T49