| T1056 |
/workspace/coverage/default/3.flash_ctrl_stress_all.3829600546 |
|
|
Jan 03 12:56:38 PM PST 24 |
Jan 03 01:05:47 PM PST 24 |
84266600 ps |
| T1057 |
/workspace/coverage/default/35.flash_ctrl_disable.1326703748 |
|
|
Jan 03 12:58:46 PM PST 24 |
Jan 03 12:59:39 PM PST 24 |
16509400 ps |
| T1058 |
/workspace/coverage/default/11.flash_ctrl_wo.2269709006 |
|
|
Jan 03 12:57:24 PM PST 24 |
Jan 03 01:01:27 PM PST 24 |
11523317500 ps |
| T408 |
/workspace/coverage/default/7.flash_ctrl_intr_wr.3681785704 |
|
|
Jan 03 12:57:18 PM PST 24 |
Jan 03 12:59:58 PM PST 24 |
4037564100 ps |
| T1059 |
/workspace/coverage/default/6.flash_ctrl_phy_arb.3533085434 |
|
|
Jan 03 12:57:13 PM PST 24 |
Jan 03 01:04:38 PM PST 24 |
1426581500 ps |
| T1060 |
/workspace/coverage/default/9.flash_ctrl_wo.2413895705 |
|
|
Jan 03 12:57:32 PM PST 24 |
Jan 03 01:00:36 PM PST 24 |
1645285600 ps |
| T207 |
/workspace/coverage/default/4.flash_ctrl_sec_cm.1421864565 |
|
|
Jan 03 12:56:56 PM PST 24 |
Jan 03 02:16:46 PM PST 24 |
1069527000 ps |
| T1061 |
/workspace/coverage/default/39.flash_ctrl_alert_test.2618506630 |
|
|
Jan 03 12:59:12 PM PST 24 |
Jan 03 01:00:19 PM PST 24 |
23645800 ps |
| T1062 |
/workspace/coverage/default/2.flash_ctrl_integrity.333978755 |
|
|
Jan 03 12:56:34 PM PST 24 |
Jan 03 01:06:13 PM PST 24 |
11349886800 ps |
| T1063 |
/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.315780870 |
|
|
Jan 03 12:57:02 PM PST 24 |
Jan 03 12:58:17 PM PST 24 |
18512300 ps |
| T1064 |
/workspace/coverage/default/5.flash_ctrl_alert_test.3525931756 |
|
|
Jan 03 12:57:13 PM PST 24 |
Jan 03 12:58:24 PM PST 24 |
43276100 ps |
| T1065 |
/workspace/coverage/default/26.flash_ctrl_prog_reset.18980228 |
|
|
Jan 03 12:58:27 PM PST 24 |
Jan 03 12:59:14 PM PST 24 |
25957100 ps |
| T1066 |
/workspace/coverage/default/6.flash_ctrl_rand_ops.4032893451 |
|
|
Jan 03 12:57:10 PM PST 24 |
Jan 03 01:01:26 PM PST 24 |
44216400 ps |
| T386 |
/workspace/coverage/default/49.flash_ctrl_sec_info_access.4075675392 |
|
|
Jan 03 12:59:06 PM PST 24 |
Jan 03 01:00:47 PM PST 24 |
1403300000 ps |
| T1067 |
/workspace/coverage/default/34.flash_ctrl_otp_reset.1159821967 |
|
|
Jan 03 12:59:08 PM PST 24 |
Jan 03 01:01:49 PM PST 24 |
39196500 ps |
| T1068 |
/workspace/coverage/default/15.flash_ctrl_mp_regions.466290509 |
|
|
Jan 03 12:57:27 PM PST 24 |
Jan 03 01:02:57 PM PST 24 |
47962768000 ps |
| T1069 |
/workspace/coverage/default/0.flash_ctrl_stress_all.112737168 |
|
|
Jan 03 12:56:34 PM PST 24 |
Jan 03 01:05:08 PM PST 24 |
397863100 ps |
| T1070 |
/workspace/coverage/default/73.flash_ctrl_connect.2142339229 |
|
|
Jan 03 12:59:07 PM PST 24 |
Jan 03 01:00:08 PM PST 24 |
25313500 ps |
| T1071 |
/workspace/coverage/default/45.flash_ctrl_sec_info_access.3300293871 |
|
|
Jan 03 12:58:53 PM PST 24 |
Jan 03 01:00:30 PM PST 24 |
3320895800 ps |
| T220 |
/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1213311189 |
|
|
Jan 03 12:56:06 PM PST 24 |
Jan 03 01:45:01 PM PST 24 |
290730689400 ps |
| T1072 |
/workspace/coverage/default/4.flash_ctrl_disable.1647087582 |
|
|
Jan 03 12:56:56 PM PST 24 |
Jan 03 12:58:21 PM PST 24 |
15577900 ps |
| T1073 |
/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1503390655 |
|
|
Jan 03 12:58:33 PM PST 24 |
Jan 03 01:02:44 PM PST 24 |
53362674200 ps |
| T1074 |
/workspace/coverage/default/8.flash_ctrl_ro_serr.3111701174 |
|
|
Jan 03 12:57:21 PM PST 24 |
Jan 03 01:00:07 PM PST 24 |
558257300 ps |
| T1075 |
/workspace/coverage/default/23.flash_ctrl_disable.1659115510 |
|
|
Jan 03 12:58:30 PM PST 24 |
Jan 03 12:59:26 PM PST 24 |
11527400 ps |
| T1076 |
/workspace/coverage/default/1.flash_ctrl_serr_address.538436267 |
|
|
Jan 03 12:56:34 PM PST 24 |
Jan 03 12:59:20 PM PST 24 |
3753238800 ps |
| T1077 |
/workspace/coverage/default/8.flash_ctrl_error_mp.550485292 |
|
|
Jan 03 12:57:19 PM PST 24 |
Jan 03 01:33:32 PM PST 24 |
6594754400 ps |
| T1078 |
/workspace/coverage/default/23.flash_ctrl_sec_info_access.3778678006 |
|
|
Jan 03 12:58:27 PM PST 24 |
Jan 03 01:00:09 PM PST 24 |
4151242600 ps |
| T1079 |
/workspace/coverage/default/32.flash_ctrl_rw_evict.1425357113 |
|
|
Jan 03 12:58:14 PM PST 24 |
Jan 03 12:59:20 PM PST 24 |
62146900 ps |
| T1080 |
/workspace/coverage/default/2.flash_ctrl_rw.3465391591 |
|
|
Jan 03 12:56:39 PM PST 24 |
Jan 03 01:05:27 PM PST 24 |
3643916100 ps |
| T1081 |
/workspace/coverage/default/6.flash_ctrl_wo.2434354769 |
|
|
Jan 03 12:56:56 PM PST 24 |
Jan 03 01:01:02 PM PST 24 |
4527784600 ps |
| T1082 |
/workspace/coverage/default/30.flash_ctrl_otp_reset.114692701 |
|
|
Jan 03 12:58:23 PM PST 24 |
Jan 03 01:01:12 PM PST 24 |
39394200 ps |
| T1083 |
/workspace/coverage/default/2.flash_ctrl_wo.748134275 |
|
|
Jan 03 12:56:41 PM PST 24 |
Jan 03 01:00:19 PM PST 24 |
4474695600 ps |
| T1084 |
/workspace/coverage/default/20.flash_ctrl_disable.650156300 |
|
|
Jan 03 12:57:35 PM PST 24 |
Jan 03 12:58:45 PM PST 24 |
22613000 ps |
| T1085 |
/workspace/coverage/default/3.flash_ctrl_smoke_hw.3942422146 |
|
|
Jan 03 12:56:46 PM PST 24 |
Jan 03 12:58:19 PM PST 24 |
60691200 ps |
| T1086 |
/workspace/coverage/default/10.flash_ctrl_disable.3489630123 |
|
|
Jan 03 12:57:17 PM PST 24 |
Jan 03 12:58:35 PM PST 24 |
28296400 ps |
| T1087 |
/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3622715107 |
|
|
Jan 03 12:58:23 PM PST 24 |
Jan 03 01:00:52 PM PST 24 |
16632274900 ps |
| T1088 |
/workspace/coverage/default/2.flash_ctrl_phy_arb.3676934371 |
|
|
Jan 03 12:56:35 PM PST 24 |
Jan 03 01:06:03 PM PST 24 |
2963886000 ps |
| T1089 |
/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.12540443 |
|
|
Jan 03 12:58:14 PM PST 24 |
Jan 03 01:01:58 PM PST 24 |
7757345800 ps |
| T1090 |
/workspace/coverage/default/0.flash_ctrl_rd_intg.494217719 |
|
|
Jan 03 12:56:34 PM PST 24 |
Jan 03 12:58:16 PM PST 24 |
135199500 ps |
| T1091 |
/workspace/coverage/default/48.flash_ctrl_smoke.3266037036 |
|
|
Jan 03 12:59:08 PM PST 24 |
Jan 03 01:01:57 PM PST 24 |
45057200 ps |
| T1092 |
/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.783276087 |
|
|
Jan 03 12:56:41 PM PST 24 |
Jan 03 01:00:19 PM PST 24 |
10020500600 ps |
| T1093 |
/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3374446461 |
|
|
Jan 03 12:58:09 PM PST 24 |
Jan 03 12:59:18 PM PST 24 |
30529500 ps |
| T151 |
/workspace/coverage/default/3.flash_ctrl_mid_op_rst.1019472689 |
|
|
Jan 03 12:56:38 PM PST 24 |
Jan 03 12:59:00 PM PST 24 |
3277182400 ps |
| T1094 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.2287611452 |
|
|
Jan 03 12:57:24 PM PST 24 |
Jan 03 12:58:31 PM PST 24 |
66311000 ps |
| T1095 |
/workspace/coverage/default/69.flash_ctrl_connect.875715607 |
|
|
Jan 03 12:59:18 PM PST 24 |
Jan 03 01:00:27 PM PST 24 |
207869300 ps |
| T1096 |
/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2472563095 |
|
|
Jan 03 12:56:31 PM PST 24 |
Jan 03 12:58:02 PM PST 24 |
39552000 ps |
| T1097 |
/workspace/coverage/default/60.flash_ctrl_connect.2290655888 |
|
|
Jan 03 12:58:58 PM PST 24 |
Jan 03 12:59:54 PM PST 24 |
29125300 ps |
| T1098 |
/workspace/coverage/default/2.flash_ctrl_error_mp.2998536356 |
|
|
Jan 03 12:56:46 PM PST 24 |
Jan 03 01:35:42 PM PST 24 |
3792062500 ps |
| T1099 |
/workspace/coverage/default/8.flash_ctrl_ro.2897992662 |
|
|
Jan 03 12:57:17 PM PST 24 |
Jan 03 01:00:14 PM PST 24 |
903779900 ps |
| T1100 |
/workspace/coverage/default/74.flash_ctrl_otp_reset.2277091519 |
|
|
Jan 03 12:59:08 PM PST 24 |
Jan 03 01:01:47 PM PST 24 |
89277500 ps |
| T1101 |
/workspace/coverage/default/5.flash_ctrl_disable.70838576 |
|
|
Jan 03 12:57:05 PM PST 24 |
Jan 03 12:58:26 PM PST 24 |
20519600 ps |
| T1102 |
/workspace/coverage/default/15.flash_ctrl_alert_test.737393777 |
|
|
Jan 03 12:57:45 PM PST 24 |
Jan 03 12:58:40 PM PST 24 |
32810700 ps |
| T1103 |
/workspace/coverage/default/6.flash_ctrl_prog_reset.774244786 |
|
|
Jan 03 12:57:02 PM PST 24 |
Jan 03 12:58:17 PM PST 24 |
38264800 ps |
| T1104 |
/workspace/coverage/default/7.flash_ctrl_prog_reset.1264778295 |
|
|
Jan 03 12:57:21 PM PST 24 |
Jan 03 12:58:29 PM PST 24 |
41586300 ps |
| T1105 |
/workspace/coverage/default/19.flash_ctrl_intr_rd.991189187 |
|
|
Jan 03 12:57:48 PM PST 24 |
Jan 03 01:00:53 PM PST 24 |
1455090300 ps |
| T1106 |
/workspace/coverage/default/15.flash_ctrl_disable.309383603 |
|
|
Jan 03 12:57:42 PM PST 24 |
Jan 03 12:58:47 PM PST 24 |
10825300 ps |
| T1107 |
/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.58054124 |
|
|
Jan 03 12:58:40 PM PST 24 |
Jan 03 01:02:19 PM PST 24 |
35787127000 ps |
| T1108 |
/workspace/coverage/default/7.flash_ctrl_phy_arb.1238442555 |
|
|
Jan 03 12:57:08 PM PST 24 |
Jan 03 12:59:54 PM PST 24 |
33769700 ps |
| T1109 |
/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.742098346 |
|
|
Jan 03 12:57:24 PM PST 24 |
Jan 03 12:58:49 PM PST 24 |
335387800 ps |
| T404 |
/workspace/coverage/default/3.flash_ctrl_fs_sup.4169716558 |
|
|
Jan 03 12:56:39 PM PST 24 |
Jan 03 12:58:23 PM PST 24 |
756070200 ps |
| T1110 |
/workspace/coverage/default/1.flash_ctrl_sw_op.1688925845 |
|
|
Jan 03 12:56:25 PM PST 24 |
Jan 03 12:58:02 PM PST 24 |
24482400 ps |
| T1111 |
/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2653933524 |
|
|
Jan 03 12:57:22 PM PST 24 |
Jan 03 12:58:29 PM PST 24 |
104329000 ps |
| T1112 |
/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.110123874 |
|
|
Jan 03 12:57:52 PM PST 24 |
Jan 03 12:59:47 PM PST 24 |
5528052200 ps |
| T1113 |
/workspace/coverage/default/9.flash_ctrl_error_mp.1569345236 |
|
|
Jan 03 12:57:47 PM PST 24 |
Jan 03 01:34:18 PM PST 24 |
10494826300 ps |
| T1114 |
/workspace/coverage/default/2.flash_ctrl_erase_suspend.2475192189 |
|
|
Jan 03 12:56:38 PM PST 24 |
Jan 03 01:02:39 PM PST 24 |
4927110100 ps |
| T1115 |
/workspace/coverage/default/20.flash_ctrl_rw_evict.426193630 |
|
|
Jan 03 12:57:34 PM PST 24 |
Jan 03 12:58:52 PM PST 24 |
27298500 ps |
| T1116 |
/workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.3351522119 |
|
|
Jan 03 12:56:18 PM PST 24 |
Jan 03 12:57:55 PM PST 24 |
104967900 ps |
| T394 |
/workspace/coverage/default/13.flash_ctrl_re_evict.3161070400 |
|
|
Jan 03 12:57:29 PM PST 24 |
Jan 03 12:58:51 PM PST 24 |
672326600 ps |
| T1117 |
/workspace/coverage/default/3.flash_ctrl_error_prog_win.4283780477 |
|
|
Jan 03 12:56:37 PM PST 24 |
Jan 03 01:11:20 PM PST 24 |
818399700 ps |
| T1118 |
/workspace/coverage/default/9.flash_ctrl_error_prog_win.1423880366 |
|
|
Jan 03 12:57:28 PM PST 24 |
Jan 03 01:13:12 PM PST 24 |
1901057900 ps |
| T1119 |
/workspace/coverage/default/4.flash_ctrl_wo.1552425881 |
|
|
Jan 03 12:56:55 PM PST 24 |
Jan 03 01:00:50 PM PST 24 |
5112234100 ps |
| T1120 |
/workspace/coverage/default/7.flash_ctrl_error_prog_win.3690837176 |
|
|
Jan 03 12:57:05 PM PST 24 |
Jan 03 01:11:03 PM PST 24 |
3692253700 ps |
| T1121 |
/workspace/coverage/default/36.flash_ctrl_connect.920897435 |
|
|
Jan 03 12:58:36 PM PST 24 |
Jan 03 12:59:24 PM PST 24 |
16262600 ps |
| T1122 |
/workspace/coverage/default/4.flash_ctrl_connect.279958713 |
|
|
Jan 03 12:56:59 PM PST 24 |
Jan 03 12:58:14 PM PST 24 |
15733600 ps |
| T1123 |
/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4250935589 |
|
|
Jan 03 12:57:00 PM PST 24 |
Jan 03 12:58:21 PM PST 24 |
95762800 ps |
| T1124 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.3786314039 |
|
|
Jan 03 12:57:02 PM PST 24 |
Jan 03 01:48:50 PM PST 24 |
2086930500 ps |
| T1125 |
/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.229449513 |
|
|
Jan 03 12:56:06 PM PST 24 |
Jan 03 12:59:40 PM PST 24 |
4380010300 ps |
| T1126 |
/workspace/coverage/default/7.flash_ctrl_ro_serr.986368410 |
|
|
Jan 03 12:57:01 PM PST 24 |
Jan 03 12:59:55 PM PST 24 |
1803323400 ps |
| T1127 |
/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1680693296 |
|
|
Jan 03 12:57:23 PM PST 24 |
Jan 03 12:58:30 PM PST 24 |
23290900 ps |
| T1128 |
/workspace/coverage/default/33.flash_ctrl_connect.1968811708 |
|
|
Jan 03 12:58:46 PM PST 24 |
Jan 03 12:59:31 PM PST 24 |
107645100 ps |
| T1129 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1208582909 |
|
|
Jan 03 12:58:14 PM PST 24 |
Jan 03 01:02:02 PM PST 24 |
8144391800 ps |
| T1130 |
/workspace/coverage/default/44.flash_ctrl_connect.2021569420 |
|
|
Jan 03 12:58:49 PM PST 24 |
Jan 03 12:59:35 PM PST 24 |
13654700 ps |
| T1131 |
/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2496191247 |
|
|
Jan 03 12:57:49 PM PST 24 |
Jan 03 01:01:45 PM PST 24 |
30585512300 ps |
| T1132 |
/workspace/coverage/default/2.flash_ctrl_host_dir_rd.224706744 |
|
|
Jan 03 12:56:44 PM PST 24 |
Jan 03 12:58:29 PM PST 24 |
26885700 ps |
| T1133 |
/workspace/coverage/default/32.flash_ctrl_smoke.1754288238 |
|
|
Jan 03 12:58:47 PM PST 24 |
Jan 03 01:01:17 PM PST 24 |
23232400 ps |
| T1134 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.3652604934 |
|
|
Jan 03 12:59:01 PM PST 24 |
Jan 03 01:01:32 PM PST 24 |
116411100 ps |
| T1135 |
/workspace/coverage/default/2.flash_ctrl_intr_wr.4009570640 |
|
|
Jan 03 12:56:36 PM PST 24 |
Jan 03 12:59:14 PM PST 24 |
3712674500 ps |
| T1136 |
/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.4024946548 |
|
|
Jan 03 12:58:08 PM PST 24 |
Jan 03 01:01:47 PM PST 24 |
13991256700 ps |
| T1137 |
/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.228715460 |
|
|
Jan 03 12:57:48 PM PST 24 |
Jan 03 12:58:59 PM PST 24 |
41054100 ps |
| T1138 |
/workspace/coverage/default/0.flash_ctrl_smoke.1636525909 |
|
|
Jan 03 12:56:17 PM PST 24 |
Jan 03 12:58:38 PM PST 24 |
21286100 ps |
| T1139 |
/workspace/coverage/default/4.flash_ctrl_fs_sup.3375109313 |
|
|
Jan 03 12:56:56 PM PST 24 |
Jan 03 12:58:35 PM PST 24 |
1135968400 ps |
| T1140 |
/workspace/coverage/default/7.flash_ctrl_alert_test.258231641 |
|
|
Jan 03 12:57:22 PM PST 24 |
Jan 03 12:58:29 PM PST 24 |
114318800 ps |
| T1141 |
/workspace/coverage/default/36.flash_ctrl_intr_rd.2515569257 |
|
|
Jan 03 12:58:33 PM PST 24 |
Jan 03 01:01:46 PM PST 24 |
1428807400 ps |
| T1142 |
/workspace/coverage/default/8.flash_ctrl_otp_reset.4176961563 |
|
|
Jan 03 12:57:29 PM PST 24 |
Jan 03 01:00:29 PM PST 24 |
42656000 ps |
| T354 |
/workspace/coverage/default/39.flash_ctrl_disable.2935518773 |
|
|
Jan 03 12:58:58 PM PST 24 |
Jan 03 12:59:59 PM PST 24 |
10441500 ps |
| T1143 |
/workspace/coverage/default/40.flash_ctrl_smoke.134992880 |
|
|
Jan 03 12:58:55 PM PST 24 |
Jan 03 01:00:23 PM PST 24 |
83948400 ps |
| T1144 |
/workspace/coverage/default/11.flash_ctrl_sec_info_access.149097987 |
|
|
Jan 03 12:57:23 PM PST 24 |
Jan 03 12:59:31 PM PST 24 |
2203901400 ps |
| T1145 |
/workspace/coverage/default/19.flash_ctrl_sec_info_access.1206535027 |
|
|
Jan 03 12:57:45 PM PST 24 |
Jan 03 12:59:32 PM PST 24 |
1557740300 ps |
| T1146 |
/workspace/coverage/default/15.flash_ctrl_phy_arb.1650107286 |
|
|
Jan 03 12:57:26 PM PST 24 |
Jan 03 01:05:46 PM PST 24 |
15274925800 ps |
| T1147 |
/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3245225440 |
|
|
Jan 03 12:57:32 PM PST 24 |
Jan 03 12:59:05 PM PST 24 |
999243300 ps |
| T1148 |
/workspace/coverage/default/19.flash_ctrl_otp_reset.3281037135 |
|
|
Jan 03 12:58:00 PM PST 24 |
Jan 03 01:00:51 PM PST 24 |
134316200 ps |
| T1149 |
/workspace/coverage/default/6.flash_ctrl_connect.1706991800 |
|
|
Jan 03 12:57:02 PM PST 24 |
Jan 03 12:58:19 PM PST 24 |
23273000 ps |
| T1150 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3225373113 |
|
|
Jan 03 12:59:01 PM PST 24 |
Jan 03 01:00:31 PM PST 24 |
563772800 ps |
| T1151 |
/workspace/coverage/default/75.flash_ctrl_connect.963781618 |
|
|
Jan 03 12:58:43 PM PST 24 |
Jan 03 12:59:28 PM PST 24 |
180346800 ps |
| T1152 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.552006251 |
|
|
Jan 03 12:58:17 PM PST 24 |
Jan 03 12:59:42 PM PST 24 |
367634900 ps |
| T1153 |
/workspace/coverage/default/59.flash_ctrl_otp_reset.2285226404 |
|
|
Jan 03 12:59:02 PM PST 24 |
Jan 03 01:01:54 PM PST 24 |
41317800 ps |
| T1154 |
/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2896415713 |
|
|
Jan 03 12:57:01 PM PST 24 |
Jan 03 12:59:03 PM PST 24 |
15899676900 ps |
| T1155 |
/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2101197473 |
|
|
Jan 03 12:57:59 PM PST 24 |
Jan 03 01:02:14 PM PST 24 |
22848567000 ps |
| T1156 |
/workspace/coverage/default/6.flash_ctrl_invalid_op.213599863 |
|
|
Jan 03 12:56:57 PM PST 24 |
Jan 03 12:59:09 PM PST 24 |
18128273300 ps |
| T1157 |
/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.744124944 |
|
|
Jan 03 12:58:36 PM PST 24 |
Jan 03 01:00:17 PM PST 24 |
2116281000 ps |
| T1158 |
/workspace/coverage/default/28.flash_ctrl_disable.2856230624 |
|
|
Jan 03 12:58:27 PM PST 24 |
Jan 03 12:59:21 PM PST 24 |
26258100 ps |
| T1159 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2305124479 |
|
|
Jan 03 12:34:40 PM PST 24 |
Jan 03 12:36:13 PM PST 24 |
14488600 ps |
| T317 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1745018101 |
|
|
Jan 03 12:36:00 PM PST 24 |
Jan 03 12:37:53 PM PST 24 |
194237700 ps |
| T340 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3986939886 |
|
|
Jan 03 12:35:11 PM PST 24 |
Jan 03 12:36:43 PM PST 24 |
15907000 ps |
| T1160 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1013420143 |
|
|
Jan 03 12:34:31 PM PST 24 |
Jan 03 12:36:12 PM PST 24 |
256340400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1245930006 |
|
|
Jan 03 12:34:42 PM PST 24 |
Jan 03 12:36:07 PM PST 24 |
50983100 ps |
| T1162 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1462057952 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:29 PM PST 24 |
27981600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.591956370 |
|
|
Jan 03 12:34:38 PM PST 24 |
Jan 03 12:36:57 PM PST 24 |
53105200 ps |
| T1164 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3822674942 |
|
|
Jan 03 12:34:55 PM PST 24 |
Jan 03 12:37:03 PM PST 24 |
15125800 ps |
| T1165 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.4165873549 |
|
|
Jan 03 12:34:28 PM PST 24 |
Jan 03 12:36:03 PM PST 24 |
46289200 ps |
| T336 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.861567725 |
|
|
Jan 03 12:35:26 PM PST 24 |
Jan 03 12:37:13 PM PST 24 |
15371200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1595640732 |
|
|
Jan 03 12:34:58 PM PST 24 |
Jan 03 12:36:47 PM PST 24 |
17618500 ps |
| T318 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4185176126 |
|
|
Jan 03 12:35:06 PM PST 24 |
Jan 03 12:36:57 PM PST 24 |
66664700 ps |
| T339 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2999388314 |
|
|
Jan 03 12:34:38 PM PST 24 |
Jan 03 12:36:00 PM PST 24 |
25990500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2751156989 |
|
|
Jan 03 12:34:19 PM PST 24 |
Jan 03 12:36:16 PM PST 24 |
153807300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3854788383 |
|
|
Jan 03 12:34:33 PM PST 24 |
Jan 03 12:36:02 PM PST 24 |
252188000 ps |
| T337 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2610781273 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:29 PM PST 24 |
17508800 ps |
| T251 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2074002969 |
|
|
Jan 03 12:34:36 PM PST 24 |
Jan 03 12:51:37 PM PST 24 |
2870189400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1352877641 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:05 PM PST 24 |
32082000 ps |
| T1170 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3729900001 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:27 PM PST 24 |
43575100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3913549924 |
|
|
Jan 03 12:33:59 PM PST 24 |
Jan 03 12:35:31 PM PST 24 |
66046800 ps |
| T1172 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3656864511 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:30 PM PST 24 |
14361800 ps |
| T1173 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1182526417 |
|
|
Jan 03 12:35:01 PM PST 24 |
Jan 03 12:36:39 PM PST 24 |
52556400 ps |
| T343 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1513593991 |
|
|
Jan 03 12:34:40 PM PST 24 |
Jan 03 12:42:39 PM PST 24 |
179028900 ps |
| T289 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1261732744 |
|
|
Jan 03 12:34:36 PM PST 24 |
Jan 03 12:50:59 PM PST 24 |
3181688500 ps |
| T319 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3248988725 |
|
|
Jan 03 12:34:07 PM PST 24 |
Jan 03 12:35:41 PM PST 24 |
243353400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1955479312 |
|
|
Jan 03 12:34:15 PM PST 24 |
Jan 03 12:36:22 PM PST 24 |
1144408700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.719556788 |
|
|
Jan 03 12:35:16 PM PST 24 |
Jan 03 12:36:59 PM PST 24 |
348854700 ps |
| T338 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.639019573 |
|
|
Jan 03 12:34:41 PM PST 24 |
Jan 03 12:36:02 PM PST 24 |
115625700 ps |
| T260 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.226161516 |
|
|
Jan 03 12:34:48 PM PST 24 |
Jan 03 12:36:20 PM PST 24 |
18363000 ps |
| T264 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.545009320 |
|
|
Jan 03 12:35:18 PM PST 24 |
Jan 03 12:37:16 PM PST 24 |
96685800 ps |
| T265 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.279353273 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:11 PM PST 24 |
37568100 ps |
| T266 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3613534752 |
|
|
Jan 03 12:34:35 PM PST 24 |
Jan 03 12:35:57 PM PST 24 |
31495000 ps |
| T267 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3213802107 |
|
|
Jan 03 12:34:43 PM PST 24 |
Jan 03 12:36:24 PM PST 24 |
55424400 ps |
| T268 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3830986570 |
|
|
Jan 03 12:35:00 PM PST 24 |
Jan 03 12:36:32 PM PST 24 |
209501500 ps |
| T269 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2401600150 |
|
|
Jan 03 12:34:46 PM PST 24 |
Jan 03 12:36:17 PM PST 24 |
47155000 ps |
| T270 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1119661204 |
|
|
Jan 03 12:34:09 PM PST 24 |
Jan 03 12:43:05 PM PST 24 |
794063900 ps |
| T271 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3648383977 |
|
|
Jan 03 12:34:40 PM PST 24 |
Jan 03 12:36:16 PM PST 24 |
38439900 ps |
| T272 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.779753756 |
|
|
Jan 03 12:34:30 PM PST 24 |
Jan 03 12:36:26 PM PST 24 |
38889700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4093213806 |
|
|
Jan 03 12:34:39 PM PST 24 |
Jan 03 12:36:03 PM PST 24 |
36258400 ps |
| T1177 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2761382687 |
|
|
Jan 03 12:34:30 PM PST 24 |
Jan 03 12:35:55 PM PST 24 |
203313500 ps |
| T1178 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.862455766 |
|
|
Jan 03 12:34:49 PM PST 24 |
Jan 03 12:36:18 PM PST 24 |
44327800 ps |
| T320 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1480897721 |
|
|
Jan 03 12:34:45 PM PST 24 |
Jan 03 12:37:13 PM PST 24 |
867337000 ps |
| T286 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1341494000 |
|
|
Jan 03 12:34:55 PM PST 24 |
Jan 03 12:36:28 PM PST 24 |
62984600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1520348828 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:27 PM PST 24 |
13106200 ps |
| T1180 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1731857809 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:18 PM PST 24 |
23008000 ps |
| T1181 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3316074107 |
|
|
Jan 03 12:34:30 PM PST 24 |
Jan 03 12:36:11 PM PST 24 |
39435800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3141617900 |
|
|
Jan 03 12:35:03 PM PST 24 |
Jan 03 12:37:06 PM PST 24 |
17150200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1050381208 |
|
|
Jan 03 12:35:02 PM PST 24 |
Jan 03 12:36:59 PM PST 24 |
44420600 ps |
| T1184 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2842277052 |
|
|
Jan 03 12:34:51 PM PST 24 |
Jan 03 12:37:08 PM PST 24 |
16322700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.915264517 |
|
|
Jan 03 12:34:16 PM PST 24 |
Jan 03 12:36:39 PM PST 24 |
2468273200 ps |
| T284 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3805549261 |
|
|
Jan 03 12:35:12 PM PST 24 |
Jan 03 12:51:42 PM PST 24 |
3067270000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1832007625 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:05 PM PST 24 |
24972200 ps |
| T1187 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3078418842 |
|
|
Jan 03 12:34:16 PM PST 24 |
Jan 03 12:36:54 PM PST 24 |
7297842700 ps |
| T324 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.822414839 |
|
|
Jan 03 12:35:19 PM PST 24 |
Jan 03 12:37:07 PM PST 24 |
35374000 ps |
| T323 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.722567818 |
|
|
Jan 03 12:34:52 PM PST 24 |
Jan 03 12:43:58 PM PST 24 |
597998700 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1249811069 |
|
|
Jan 03 12:35:13 PM PST 24 |
Jan 03 12:36:54 PM PST 24 |
21949300 ps |
| T285 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3080662198 |
|
|
Jan 03 12:34:42 PM PST 24 |
Jan 03 12:48:34 PM PST 24 |
1917867200 ps |
| T1189 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2265986429 |
|
|
Jan 03 12:34:50 PM PST 24 |
Jan 03 12:36:23 PM PST 24 |
29491300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1416359491 |
|
|
Jan 03 12:34:40 PM PST 24 |
Jan 03 12:36:04 PM PST 24 |
44551500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2296743454 |
|
|
Jan 03 12:34:28 PM PST 24 |
Jan 03 12:36:07 PM PST 24 |
181990200 ps |
| T1192 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.4155672612 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:14 PM PST 24 |
139075400 ps |
| T282 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.462983446 |
|
|
Jan 03 12:35:03 PM PST 24 |
Jan 03 12:36:38 PM PST 24 |
112122500 ps |
| T288 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1449485793 |
|
|
Jan 03 12:34:39 PM PST 24 |
Jan 03 12:36:16 PM PST 24 |
122133400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3027670180 |
|
|
Jan 03 12:34:28 PM PST 24 |
Jan 03 12:36:00 PM PST 24 |
67052200 ps |
| T287 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.909576496 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:20 PM PST 24 |
113669700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.154336119 |
|
|
Jan 03 12:34:41 PM PST 24 |
Jan 03 12:36:13 PM PST 24 |
101343100 ps |
| T261 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2530523303 |
|
|
Jan 03 12:34:24 PM PST 24 |
Jan 03 12:35:59 PM PST 24 |
15974300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3195902032 |
|
|
Jan 03 12:34:43 PM PST 24 |
Jan 03 12:36:24 PM PST 24 |
18399600 ps |
| T325 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1005818723 |
|
|
Jan 03 12:34:48 PM PST 24 |
Jan 03 12:37:11 PM PST 24 |
869375200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.598082536 |
|
|
Jan 03 12:34:34 PM PST 24 |
Jan 03 12:36:00 PM PST 24 |
20347300 ps |
| T1197 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3230041944 |
|
|
Jan 03 12:34:26 PM PST 24 |
Jan 03 12:35:57 PM PST 24 |
52262500 ps |
| T1198 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3022329645 |
|
|
Jan 03 12:34:59 PM PST 24 |
Jan 03 12:36:55 PM PST 24 |
95666400 ps |
| T347 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1102680564 |
|
|
Jan 03 12:34:42 PM PST 24 |
Jan 03 12:43:38 PM PST 24 |
1375469500 ps |
| T1199 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3554048277 |
|
|
Jan 03 12:35:08 PM PST 24 |
Jan 03 12:37:05 PM PST 24 |
15162500 ps |
| T283 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2558800420 |
|
|
Jan 03 12:34:33 PM PST 24 |
Jan 03 12:36:26 PM PST 24 |
54078700 ps |
| T1200 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4132061376 |
|
|
Jan 03 12:35:18 PM PST 24 |
Jan 03 12:37:02 PM PST 24 |
12377800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.586211511 |
|
|
Jan 03 12:34:50 PM PST 24 |
Jan 03 12:36:37 PM PST 24 |
30632900 ps |
| T290 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3514807726 |
|
|
Jan 03 12:36:00 PM PST 24 |
Jan 03 12:37:54 PM PST 24 |
82378800 ps |
| T1202 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1141907133 |
|
|
Jan 03 12:34:48 PM PST 24 |
Jan 03 12:36:16 PM PST 24 |
128555400 ps |
| T1203 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.695502696 |
|
|
Jan 03 12:34:12 PM PST 24 |
Jan 03 12:36:07 PM PST 24 |
322968900 ps |
| T1204 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1374631928 |
|
|
Jan 03 12:34:31 PM PST 24 |
Jan 03 12:36:06 PM PST 24 |
131082900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.592679952 |
|
|
Jan 03 12:35:08 PM PST 24 |
Jan 03 12:37:03 PM PST 24 |
227790400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2478416154 |
|
|
Jan 03 12:35:13 PM PST 24 |
Jan 03 12:36:53 PM PST 24 |
43010600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1524568627 |
|
|
Jan 03 12:35:12 PM PST 24 |
Jan 03 12:36:58 PM PST 24 |
90990800 ps |
| T1208 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1674984229 |
|
|
Jan 03 12:35:03 PM PST 24 |
Jan 03 12:36:34 PM PST 24 |
12524700 ps |
| T1209 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1170710593 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:33 PM PST 24 |
168245900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3535054972 |
|
|
Jan 03 12:34:18 PM PST 24 |
Jan 03 12:35:52 PM PST 24 |
14343800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2857269774 |
|
|
Jan 03 12:34:43 PM PST 24 |
Jan 03 12:36:45 PM PST 24 |
93826000 ps |
| T1212 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2384403552 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:14 PM PST 24 |
93874700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2360132062 |
|
|
Jan 03 12:34:33 PM PST 24 |
Jan 03 12:36:21 PM PST 24 |
326615500 ps |
| T1214 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.98179870 |
|
|
Jan 03 12:35:24 PM PST 24 |
Jan 03 12:37:13 PM PST 24 |
23115800 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.355858554 |
|
|
Jan 03 12:34:52 PM PST 24 |
Jan 03 12:36:18 PM PST 24 |
15225600 ps |
| T342 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2874312411 |
|
|
Jan 03 12:34:55 PM PST 24 |
Jan 03 12:52:10 PM PST 24 |
1340000100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.799553246 |
|
|
Jan 03 12:34:39 PM PST 24 |
Jan 03 12:35:59 PM PST 24 |
109602600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3155759090 |
|
|
Jan 03 12:35:27 PM PST 24 |
Jan 03 12:37:11 PM PST 24 |
24393300 ps |
| T348 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1268191098 |
|
|
Jan 03 12:34:45 PM PST 24 |
Jan 03 12:51:58 PM PST 24 |
1400615000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4256320775 |
|
|
Jan 03 12:34:29 PM PST 24 |
Jan 03 12:36:03 PM PST 24 |
15504400 ps |
| T1219 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3194255773 |
|
|
Jan 03 12:34:52 PM PST 24 |
Jan 03 12:36:28 PM PST 24 |
38512300 ps |
| T346 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3595310337 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:44:05 PM PST 24 |
3424847200 ps |
| T1220 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1988445404 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:27 PM PST 24 |
18316400 ps |
| T345 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2704276004 |
|
|
Jan 03 12:34:50 PM PST 24 |
Jan 03 12:51:07 PM PST 24 |
764756900 ps |
| T1221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2858414086 |
|
|
Jan 03 12:34:50 PM PST 24 |
Jan 03 12:36:39 PM PST 24 |
457857700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.965650840 |
|
|
Jan 03 12:34:20 PM PST 24 |
Jan 03 12:35:56 PM PST 24 |
31709800 ps |
| T344 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1191467599 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:43:51 PM PST 24 |
717637100 ps |
| T1223 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1163153207 |
|
|
Jan 03 12:34:48 PM PST 24 |
Jan 03 12:36:25 PM PST 24 |
123289000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3972296971 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:10 PM PST 24 |
37944300 ps |
| T291 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3459992863 |
|
|
Jan 03 12:34:44 PM PST 24 |
Jan 03 12:36:12 PM PST 24 |
26732100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1671563126 |
|
|
Jan 03 12:33:57 PM PST 24 |
Jan 03 12:35:47 PM PST 24 |
24606600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.382063685 |
|
|
Jan 03 12:34:07 PM PST 24 |
Jan 03 12:36:02 PM PST 24 |
832082300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4248381249 |
|
|
Jan 03 12:34:28 PM PST 24 |
Jan 03 12:36:05 PM PST 24 |
46379000 ps |
| T1228 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3689317657 |
|
|
Jan 03 12:35:03 PM PST 24 |
Jan 03 12:37:07 PM PST 24 |
19069400 ps |
| T1229 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1509119272 |
|
|
Jan 03 12:34:32 PM PST 24 |
Jan 03 12:36:17 PM PST 24 |
264777400 ps |
| T1230 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1103890817 |
|
|
Jan 03 12:34:51 PM PST 24 |
Jan 03 12:37:04 PM PST 24 |
17089100 ps |
| T1231 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.915059111 |
|
|
Jan 03 12:34:59 PM PST 24 |
Jan 03 12:36:55 PM PST 24 |
30283900 ps |
| T1232 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4195556361 |
|
|
Jan 03 12:34:00 PM PST 24 |
Jan 03 12:35:52 PM PST 24 |
40807400 ps |
| T1233 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.409985695 |
|
|
Jan 03 12:34:36 PM PST 24 |
Jan 03 12:36:17 PM PST 24 |
34598000 ps |
| T326 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1213967314 |
|
|
Jan 03 12:35:15 PM PST 24 |
Jan 03 12:37:00 PM PST 24 |
47733600 ps |
| T1234 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3827165528 |
|
|
Jan 03 12:34:49 PM PST 24 |
Jan 03 12:36:19 PM PST 24 |
37404600 ps |
| T1235 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.530267754 |
|
|
Jan 03 12:34:33 PM PST 24 |
Jan 03 12:36:44 PM PST 24 |
193913900 ps |
| T1236 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.619885663 |
|
|
Jan 03 12:34:45 PM PST 24 |
Jan 03 12:36:19 PM PST 24 |
279226000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3010083125 |
|
|
Jan 03 12:34:20 PM PST 24 |
Jan 03 12:35:49 PM PST 24 |
32185100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4039161483 |
|
|
Jan 03 12:34:32 PM PST 24 |
Jan 03 12:35:55 PM PST 24 |
25288700 ps |
| T1239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.617141727 |
|
|
Jan 03 12:35:26 PM PST 24 |
Jan 03 12:37:13 PM PST 24 |
12035500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.778894082 |
|
|
Jan 03 12:34:16 PM PST 24 |
Jan 03 12:35:59 PM PST 24 |
33496200 ps |
| T262 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1720777577 |
|
|
Jan 03 12:34:30 PM PST 24 |
Jan 03 12:36:04 PM PST 24 |
53486900 ps |
| T1241 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.230191770 |
|
|
Jan 03 12:35:07 PM PST 24 |
Jan 03 12:36:38 PM PST 24 |
72350500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2146651474 |
|
|
Jan 03 12:34:45 PM PST 24 |
Jan 03 12:51:12 PM PST 24 |
1640127300 ps |
| T1243 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2358800859 |
|
|
Jan 03 12:35:23 PM PST 24 |
Jan 03 12:37:12 PM PST 24 |
53488000 ps |
| T1244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3311470165 |
|
|
Jan 03 12:34:31 PM PST 24 |
Jan 03 12:35:52 PM PST 24 |
24247400 ps |
| T327 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1510292121 |
|
|
Jan 03 12:35:16 PM PST 24 |
Jan 03 12:36:59 PM PST 24 |
215920000 ps |
| T328 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1331932691 |
|
|
Jan 03 12:34:20 PM PST 24 |
Jan 03 12:36:13 PM PST 24 |
51371700 ps |
| T1245 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2973764532 |
|
|
Jan 03 12:34:47 PM PST 24 |
Jan 03 12:36:19 PM PST 24 |
52647900 ps |
| T1246 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1506152502 |
|
|
Jan 03 12:34:57 PM PST 24 |
Jan 03 12:37:11 PM PST 24 |
198143400 ps |
| T1247 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3995185023 |
|
|
Jan 03 12:35:05 PM PST 24 |
Jan 03 12:36:59 PM PST 24 |
213715100 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2951555687 |
|
|
Jan 03 12:34:58 PM PST 24 |
Jan 03 12:37:00 PM PST 24 |
78970000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2717972007 |
|
|
Jan 03 12:34:34 PM PST 24 |
Jan 03 12:36:24 PM PST 24 |
127814700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4101651880 |
|
|
Jan 03 12:35:06 PM PST 24 |
Jan 03 12:36:57 PM PST 24 |
131311700 ps |
| T1251 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3079268842 |
|
|
Jan 03 12:34:42 PM PST 24 |
Jan 03 12:36:15 PM PST 24 |
53366600 ps |
| T1252 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2260149414 |
|
|
Jan 03 12:34:45 PM PST 24 |
Jan 03 12:36:19 PM PST 24 |
23490000 ps |