Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	254805	1		T23	5		T63	1		T64	5
all_values[1]	254805	1		T23	5		T63	1		T64	5
all_values[2]	254805	1		T23	5		T63	1		T64	5
all_values[3]	254805	1		T23	5		T63	1		T64	5
all_values[4]	254805	1		T23	5		T63	1		T64	5
all_values[5]	254805	1		T23	5		T63	1		T64	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	8552	1		T23	14		T63	6		T64	17
auto[1]	1520278	1		T23	16		T64	13		T230	22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1240510	1		T23	13		T63	6		T64	20
auto[1]	288320	1		T23	17		T64	10		T230	24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1072	1		T63	1		T64	3		T67	1
all_values[0]	auto[0]	auto[1]	349	1		T23	2		T64	2		T230	2
all_values[0]	auto[1]	auto[0]	209131	1		T23	1		T230	1		T224	1
all_values[0]	auto[1]	auto[1]	44253	1		T23	2		T230	5		T275	3
all_values[1]	auto[0]	auto[0]	1358	1		T23	1		T63	1		T64	1
all_values[1]	auto[0]	auto[1]	73	1		T23	2		T275	1		T224	2
all_values[1]	auto[1]	auto[0]	207067	1		T23	1		T64	4		T230	1
all_values[1]	auto[1]	auto[1]	46307	1		T23	1		T230	1		T224	2
all_values[2]	auto[0]	auto[0]	1310	1		T63	1		T64	1		T67	1
all_values[2]	auto[0]	auto[1]	101	1		T64	2		T230	2		T275	4
all_values[2]	auto[1]	auto[0]	248961	1		T23	4		T64	2		T230	2
all_values[2]	auto[1]	auto[1]	4433	1		T23	1		T275	2		T224	4
all_values[3]	auto[0]	auto[0]	1310	1		T63	1		T64	1		T67	1
all_values[3]	auto[0]	auto[1]	124	1		T64	2		T275	1		T224	3
all_values[3]	auto[1]	auto[0]	140588	1		T23	1		T230	2		T231	5
all_values[3]	auto[1]	auto[1]	112783	1		T23	4		T64	2		T230	5
all_values[4]	auto[0]	auto[0]	1003	1		T23	2		T63	1		T64	3
all_values[4]	auto[0]	auto[1]	433	1		T23	3		T230	3		T334	3
all_values[4]	auto[1]	auto[0]	174111	1		T64	1		T230	3		T231	3
all_values[4]	auto[1]	auto[1]	79258	1		T64	1		T230	1		T231	2
all_values[5]	auto[0]	auto[0]	1279	1		T23	2		T63	1		T64	1
all_values[5]	auto[0]	auto[1]	140	1		T23	2		T64	1		T230	4
all_values[5]	auto[1]	auto[0]	253320	1		T23	1		T64	3		T231	2
all_values[5]	auto[1]	auto[1]	66	1		T230	1		T231	2		T275	4