Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
179 |
1 |
|
T21 |
1 |
|
T196 |
1 |
|
T76 |
1 |
| others[1] |
168 |
1 |
|
T7 |
1 |
|
T118 |
1 |
|
T35 |
1 |
| others[2] |
184 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T20 |
1 |
| others[3] |
297 |
1 |
|
T17 |
1 |
|
T44 |
1 |
|
T51 |
1 |
| false |
97 |
1 |
|
T189 |
1 |
|
T121 |
1 |
|
T140 |
1 |
| true |
10891 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
162 |
1 |
|
T123 |
8 |
|
T376 |
1 |
|
T377 |
1 |
| others[1] |
154 |
1 |
|
T357 |
1 |
|
T87 |
1 |
|
T221 |
1 |
| others[2] |
164 |
1 |
|
T118 |
1 |
|
T189 |
1 |
|
T361 |
1 |
| others[3] |
291 |
1 |
|
T46 |
1 |
|
T35 |
1 |
|
T140 |
3 |
| false |
81 |
1 |
|
T188 |
1 |
|
T123 |
2 |
|
T73 |
2 |
| true |
10964 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7377 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| others[1] |
999 |
1 |
|
T275 |
1 |
|
T312 |
1 |
|
T148 |
1 |
| others[2] |
924 |
1 |
|
T231 |
1 |
|
T225 |
1 |
|
T226 |
1 |
| others[3] |
1644 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| false |
494 |
1 |
|
T3 |
8 |
|
T33 |
3 |
|
T220 |
1 |
| true |
378 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7353 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T275 |
1 |
| others[1] |
972 |
1 |
|
T335 |
1 |
|
T289 |
1 |
|
T295 |
1 |
| others[2] |
995 |
1 |
|
T23 |
1 |
|
T231 |
1 |
|
T225 |
1 |
| others[3] |
1666 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T144 |
1 |
| false |
475 |
1 |
|
T292 |
1 |
|
T370 |
1 |
|
T3 |
12 |
| true |
355 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
75 |
1 |
|
T34 |
2 |
|
T140 |
1 |
|
T359 |
1 |
| others[1] |
71 |
1 |
|
T140 |
1 |
|
T368 |
1 |
|
T123 |
6 |
| others[2] |
77 |
1 |
|
T17 |
1 |
|
T46 |
1 |
|
T140 |
1 |
| others[3] |
120 |
1 |
|
T47 |
1 |
|
T140 |
5 |
|
T359 |
1 |
| false |
46 |
1 |
|
T76 |
1 |
|
T123 |
4 |
|
T376 |
1 |
| true |
11427 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
175 |
1 |
|
T46 |
1 |
|
T84 |
1 |
|
T9 |
1 |
| others[1] |
159 |
1 |
|
T9 |
1 |
|
T140 |
1 |
|
T123 |
10 |
| others[2] |
188 |
1 |
|
T76 |
1 |
|
T357 |
1 |
|
T121 |
1 |
| others[3] |
332 |
1 |
|
T17 |
1 |
|
T47 |
1 |
|
T21 |
1 |
| false |
83 |
1 |
|
T162 |
1 |
|
T237 |
1 |
|
T123 |
6 |
| true |
10879 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7182 |
1 |
|
T23 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| others[1] |
810 |
1 |
|
T143 |
1 |
|
T230 |
1 |
|
T226 |
1 |
| others[2] |
885 |
1 |
|
T335 |
1 |
|
T370 |
1 |
|
T149 |
1 |
| others[3] |
1378 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| false |
437 |
1 |
|
T312 |
1 |
|
T3 |
4 |
|
T188 |
1 |
| true |
1124 |
1 |
|
T3 |
46 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
190 |
1 |
|
T50 |
1 |
|
T44 |
1 |
|
T188 |
1 |
| others[1] |
157 |
1 |
|
T47 |
1 |
|
T357 |
1 |
|
T221 |
1 |
| others[2] |
174 |
1 |
|
T7 |
1 |
|
T140 |
2 |
|
T322 |
1 |
| others[3] |
286 |
1 |
|
T1 |
1 |
|
T46 |
1 |
|
T21 |
1 |
| false |
84 |
1 |
|
T34 |
1 |
|
T140 |
1 |
|
T359 |
1 |
| true |
10925 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
159 |
1 |
|
T140 |
1 |
|
T237 |
1 |
|
T123 |
13 |
| others[1] |
191 |
1 |
|
T118 |
1 |
|
T140 |
1 |
|
T368 |
1 |
| others[2] |
165 |
1 |
|
T17 |
1 |
|
T357 |
1 |
|
T140 |
2 |
| others[3] |
266 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T9 |
3 |
| false |
86 |
1 |
|
T189 |
1 |
|
T76 |
1 |
|
T221 |
1 |
| true |
10949 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7364 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T224 |
1 |
| others[1] |
954 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T225 |
1 |
| others[2] |
971 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T370 |
1 |
| others[3] |
1627 |
1 |
|
T230 |
1 |
|
T231 |
1 |
|
T275 |
1 |
| false |
531 |
1 |
|
T335 |
1 |
|
T295 |
1 |
|
T149 |
1 |
| true |
369 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
951 |
1 |
|
T370 |
1 |
|
T281 |
1 |
|
T3 |
11 |
| others[1] |
974 |
1 |
|
T230 |
1 |
|
T334 |
1 |
|
T335 |
1 |
| others[2] |
984 |
1 |
|
T144 |
1 |
|
T312 |
1 |
|
T373 |
1 |
| others[3] |
1693 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T67 |
1 |
| false |
495 |
1 |
|
T64 |
1 |
|
T289 |
1 |
|
T3 |
12 |
| true |
350 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T35 |
1 |
|
T140 |
2 |
|
T123 |
7 |
| others[1] |
75 |
1 |
|
T140 |
1 |
|
T364 |
1 |
|
T123 |
2 |
| others[2] |
59 |
1 |
|
T359 |
1 |
|
T363 |
1 |
|
T367 |
1 |
| others[3] |
129 |
1 |
|
T34 |
2 |
|
T140 |
4 |
|
T368 |
1 |
| false |
34 |
1 |
|
T140 |
1 |
|
T359 |
1 |
|
T123 |
1 |
| true |
5058 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
165 |
1 |
|
T20 |
1 |
|
T84 |
1 |
|
T76 |
1 |
| others[1] |
185 |
1 |
|
T47 |
1 |
|
T189 |
1 |
|
T140 |
1 |
| others[2] |
185 |
1 |
|
T116 |
1 |
|
T118 |
1 |
|
T53 |
1 |
| others[3] |
281 |
1 |
|
T19 |
1 |
|
T51 |
1 |
|
T196 |
1 |
| false |
95 |
1 |
|
T46 |
1 |
|
T87 |
1 |
|
T361 |
1 |
| true |
4536 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
897 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T294 |
1 |
| others[1] |
792 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T231 |
1 |
| others[2] |
883 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T224 |
1 |
| others[3] |
1284 |
1 |
|
T143 |
1 |
|
T334 |
1 |
|
T225 |
1 |
| false |
433 |
1 |
|
T275 |
1 |
|
T3 |
5 |
|
T49 |
1 |
| true |
1158 |
1 |
|
T1 |
1 |
|
T3 |
46 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
150 |
1 |
|
T4 |
1 |
|
T140 |
2 |
|
T123 |
17 |
| others[1] |
196 |
1 |
|
T118 |
1 |
|
T262 |
1 |
|
T237 |
1 |
| others[2] |
149 |
1 |
|
T188 |
1 |
|
T256 |
1 |
|
T361 |
1 |
| others[3] |
293 |
1 |
|
T17 |
1 |
|
T46 |
1 |
|
T7 |
1 |
| false |
98 |
1 |
|
T50 |
1 |
|
T76 |
1 |
|
T123 |
5 |
| true |
4561 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
158 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T361 |
1 |
| others[1] |
185 |
1 |
|
T47 |
1 |
|
T9 |
1 |
|
T140 |
1 |
| others[2] |
158 |
1 |
|
T188 |
1 |
|
T53 |
1 |
|
T363 |
1 |
| others[3] |
271 |
1 |
|
T35 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| false |
75 |
1 |
|
T9 |
2 |
|
T368 |
1 |
|
T123 |
3 |
| true |
4600 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1010 |
1 |
|
T63 |
1 |
|
T230 |
1 |
|
T224 |
1 |
| others[1] |
941 |
1 |
|
T67 |
1 |
|
T144 |
1 |
|
T225 |
1 |
| others[2] |
967 |
1 |
|
T335 |
1 |
|
T289 |
1 |
|
T295 |
1 |
| others[3] |
1626 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T143 |
1 |
| false |
535 |
1 |
|
T275 |
1 |
|
T292 |
1 |
|
T3 |
10 |
| true |
368 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
945 |
1 |
|
T275 |
1 |
|
T224 |
1 |
|
T334 |
1 |
| others[1] |
1008 |
1 |
|
T23 |
1 |
|
T312 |
1 |
|
T225 |
1 |
| others[2] |
966 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T148 |
1 |
| others[3] |
1678 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| false |
512 |
1 |
|
T294 |
1 |
|
T149 |
1 |
|
T366 |
1 |
| true |
338 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
85 |
1 |
|
T34 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| others[1] |
79 |
1 |
|
T34 |
1 |
|
T140 |
3 |
|
T123 |
2 |
| others[2] |
92 |
1 |
|
T367 |
1 |
|
T237 |
1 |
|
T123 |
5 |
| others[3] |
107 |
1 |
|
T140 |
1 |
|
T359 |
1 |
|
T364 |
1 |
| false |
46 |
1 |
|
T140 |
2 |
|
T123 |
2 |
|
T73 |
6 |
| true |
5038 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
162 |
1 |
|
T17 |
1 |
|
T49 |
1 |
|
T50 |
1 |
| others[1] |
200 |
1 |
|
T4 |
1 |
|
T47 |
1 |
|
T84 |
1 |
| others[2] |
195 |
1 |
|
T46 |
1 |
|
T9 |
1 |
|
T117 |
1 |
| others[3] |
283 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T7 |
1 |
| false |
79 |
1 |
|
T9 |
1 |
|
T221 |
1 |
|
T91 |
1 |
| true |
4528 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
831 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T144 |
1 |
| others[1] |
855 |
1 |
|
T63 |
1 |
|
T224 |
1 |
|
T312 |
1 |
| others[2] |
770 |
1 |
|
T225 |
1 |
|
T3 |
9 |
|
T7 |
1 |
| others[3] |
1344 |
1 |
|
T23 |
1 |
|
T143 |
1 |
|
T230 |
1 |
| false |
463 |
1 |
|
T231 |
1 |
|
T3 |
2 |
|
T50 |
1 |
| true |
1184 |
1 |
|
T1 |
1 |
|
T3 |
49 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
158 |
1 |
|
T17 |
1 |
|
T21 |
1 |
|
T34 |
1 |
| others[1] |
170 |
1 |
|
T35 |
1 |
|
T140 |
1 |
|
T259 |
1 |
| others[2] |
170 |
1 |
|
T50 |
1 |
|
T196 |
1 |
|
T120 |
1 |
| others[3] |
286 |
1 |
|
T1 |
1 |
|
T140 |
3 |
|
T323 |
1 |
| false |
119 |
1 |
|
T121 |
1 |
|
T368 |
1 |
|
T123 |
7 |
| true |
4544 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
174 |
1 |
|
T47 |
1 |
|
T188 |
1 |
|
T359 |
2 |
| others[1] |
165 |
1 |
|
T76 |
1 |
|
T361 |
1 |
|
T221 |
1 |
| others[2] |
159 |
1 |
|
T34 |
1 |
|
T9 |
1 |
|
T140 |
1 |
| others[3] |
316 |
1 |
|
T20 |
1 |
|
T9 |
2 |
|
T140 |
4 |
| false |
75 |
1 |
|
T87 |
1 |
|
T364 |
1 |
|
T123 |
3 |
| true |
4558 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
985 |
1 |
|
T67 |
1 |
|
T144 |
1 |
|
T312 |
1 |
| others[1] |
986 |
1 |
|
T370 |
1 |
|
T365 |
1 |
|
T366 |
1 |
| others[2] |
961 |
1 |
|
T143 |
1 |
|
T231 |
1 |
|
T334 |
1 |
| others[3] |
1644 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| false |
510 |
1 |
|
T230 |
1 |
|
T224 |
1 |
|
T3 |
9 |
| true |
361 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
999 |
1 |
|
T63 |
1 |
|
T295 |
1 |
|
T370 |
1 |
| others[1] |
957 |
1 |
|
T64 |
1 |
|
T230 |
1 |
|
T225 |
1 |
| others[2] |
1029 |
1 |
|
T275 |
1 |
|
T334 |
1 |
|
T294 |
1 |
| others[3] |
1597 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T143 |
1 |
| false |
517 |
1 |
|
T231 |
1 |
|
T148 |
1 |
|
T289 |
1 |
| true |
348 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
85 |
1 |
|
T17 |
1 |
|
T34 |
1 |
|
T188 |
1 |
| others[1] |
76 |
1 |
|
T34 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| others[2] |
79 |
1 |
|
T53 |
1 |
|
T140 |
3 |
|
T123 |
3 |
| others[3] |
132 |
1 |
|
T123 |
8 |
|
T376 |
1 |
|
T374 |
1 |
| false |
39 |
1 |
|
T359 |
1 |
|
T363 |
1 |
|
T123 |
2 |
| true |
5036 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
168 |
1 |
|
T76 |
1 |
|
T123 |
9 |
|
T358 |
1 |
| others[1] |
172 |
1 |
|
T17 |
1 |
|
T35 |
1 |
|
T203 |
1 |
| others[2] |
197 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T116 |
1 |
| others[3] |
280 |
1 |
|
T50 |
1 |
|
T51 |
1 |
|
T9 |
1 |
| false |
118 |
1 |
|
T188 |
1 |
|
T123 |
8 |
|
T73 |
1 |
| true |
4512 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
824 |
1 |
|
T23 |
1 |
|
T143 |
1 |
|
T231 |
1 |
| others[1] |
817 |
1 |
|
T275 |
1 |
|
T335 |
1 |
|
T226 |
1 |
| others[2] |
881 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| others[3] |
1400 |
1 |
|
T224 |
1 |
|
T334 |
1 |
|
T312 |
1 |
| false |
400 |
1 |
|
T230 |
1 |
|
T3 |
9 |
|
T4 |
1 |
| true |
1125 |
1 |
|
T1 |
1 |
|
T3 |
46 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T53 |
1 |
|
T203 |
1 |
|
T140 |
1 |
| others[1] |
179 |
1 |
|
T4 |
1 |
|
T76 |
1 |
|
T35 |
1 |
| others[2] |
170 |
1 |
|
T21 |
1 |
|
T196 |
1 |
|
T121 |
1 |
| others[3] |
306 |
1 |
|
T1 |
1 |
|
T46 |
1 |
|
T7 |
1 |
| false |
103 |
1 |
|
T140 |
1 |
|
T363 |
1 |
|
T123 |
3 |
| true |
4493 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
125 |
1 |
|
T9 |
2 |
|
T140 |
1 |
|
T363 |
1 |
| others[1] |
171 |
1 |
|
T4 |
1 |
|
T188 |
1 |
|
T189 |
1 |
| others[2] |
165 |
1 |
|
T20 |
1 |
|
T34 |
2 |
|
T9 |
1 |
| others[3] |
266 |
1 |
|
T9 |
1 |
|
T140 |
2 |
|
T364 |
1 |
| false |
89 |
1 |
|
T87 |
1 |
|
T123 |
7 |
|
T376 |
1 |
| true |
4631 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
975 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T225 |
1 |
| others[1] |
1028 |
1 |
|
T231 |
1 |
|
T149 |
1 |
|
T369 |
1 |
| others[2] |
1002 |
1 |
|
T143 |
1 |
|
T295 |
1 |
|
T373 |
1 |
| others[3] |
1550 |
1 |
|
T23 |
1 |
|
T275 |
1 |
|
T224 |
1 |
| false |
527 |
1 |
|
T63 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| true |
365 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |