Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T67 |
1 |
|
T275 |
1 |
|
T334 |
1 |
| others[1] |
974 |
1 |
|
T143 |
1 |
|
T335 |
1 |
|
T289 |
1 |
| others[2] |
967 |
1 |
|
T23 |
1 |
|
T312 |
1 |
|
T365 |
1 |
| others[3] |
1626 |
1 |
|
T231 |
1 |
|
T224 |
1 |
|
T149 |
1 |
| false |
497 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T144 |
1 |
| true |
344 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
66 |
1 |
|
T140 |
2 |
|
T368 |
1 |
|
T123 |
3 |
| others[1] |
91 |
1 |
|
T361 |
1 |
|
T140 |
1 |
|
T359 |
1 |
| others[2] |
75 |
1 |
|
T34 |
1 |
|
T140 |
1 |
|
T363 |
1 |
| others[3] |
136 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T357 |
1 |
| false |
43 |
1 |
|
T53 |
1 |
|
T140 |
1 |
|
T359 |
1 |
| true |
5036 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
163 |
1 |
|
T20 |
1 |
|
T84 |
1 |
|
T162 |
1 |
| others[1] |
155 |
1 |
|
T44 |
1 |
|
T21 |
1 |
|
T357 |
1 |
| others[2] |
201 |
1 |
|
T118 |
1 |
|
T53 |
1 |
|
T361 |
1 |
| others[3] |
297 |
1 |
|
T4 |
1 |
|
T50 |
1 |
|
T34 |
1 |
| false |
97 |
1 |
|
T121 |
1 |
|
T123 |
11 |
|
T73 |
6 |
| true |
4534 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
878 |
1 |
|
T144 |
1 |
|
T148 |
1 |
|
T289 |
1 |
| others[1] |
782 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T226 |
1 |
| others[2] |
796 |
1 |
|
T231 |
1 |
|
T275 |
1 |
|
T334 |
1 |
| others[3] |
1413 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T230 |
1 |
| false |
416 |
1 |
|
T143 |
1 |
|
T224 |
1 |
|
T3 |
3 |
| true |
1162 |
1 |
|
T3 |
46 |
|
T17 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
167 |
1 |
|
T120 |
1 |
|
T123 |
12 |
|
T378 |
1 |
| others[1] |
174 |
1 |
|
T1 |
1 |
|
T47 |
1 |
|
T140 |
1 |
| others[2] |
200 |
1 |
|
T21 |
1 |
|
T118 |
1 |
|
T189 |
1 |
| others[3] |
312 |
1 |
|
T17 |
1 |
|
T44 |
1 |
|
T51 |
1 |
| false |
78 |
1 |
|
T7 |
1 |
|
T76 |
1 |
|
T123 |
3 |
| true |
4516 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
189 |
1 |
|
T9 |
1 |
|
T118 |
1 |
|
T189 |
1 |
| others[1] |
175 |
1 |
|
T4 |
1 |
|
T357 |
1 |
|
T140 |
2 |
| others[2] |
131 |
1 |
|
T53 |
1 |
|
T87 |
1 |
|
T123 |
6 |
| others[3] |
283 |
1 |
|
T46 |
1 |
|
T20 |
1 |
|
T9 |
1 |
| false |
80 |
1 |
|
T9 |
1 |
|
T123 |
3 |
|
T376 |
1 |
| true |
4589 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
978 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| others[1] |
965 |
1 |
|
T64 |
1 |
|
T275 |
1 |
|
T3 |
16 |
| others[2] |
965 |
1 |
|
T224 |
1 |
|
T335 |
1 |
|
T226 |
1 |
| others[3] |
1682 |
1 |
|
T23 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| false |
489 |
1 |
|
T63 |
1 |
|
T312 |
1 |
|
T225 |
1 |
| true |
368 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
971 |
1 |
|
T230 |
1 |
|
T231 |
1 |
|
T275 |
1 |
| others[1] |
996 |
1 |
|
T63 |
1 |
|
T225 |
1 |
|
T226 |
1 |
| others[2] |
1011 |
1 |
|
T64 |
1 |
|
T312 |
1 |
|
T369 |
1 |
| others[3] |
1618 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T224 |
1 |
| false |
501 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T365 |
1 |
| true |
350 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
74 |
1 |
|
T140 |
1 |
|
T359 |
1 |
|
T368 |
1 |
| others[1] |
76 |
1 |
|
T53 |
1 |
|
T140 |
2 |
|
T237 |
1 |
| others[2] |
76 |
1 |
|
T34 |
1 |
|
T363 |
1 |
|
T367 |
1 |
| others[3] |
135 |
1 |
|
T140 |
5 |
|
T359 |
1 |
|
T364 |
1 |
| false |
34 |
1 |
|
T34 |
1 |
|
T123 |
1 |
|
T372 |
1 |
| true |
5052 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
173 |
1 |
|
T47 |
1 |
|
T51 |
1 |
|
T9 |
1 |
| others[1] |
184 |
1 |
|
T84 |
1 |
|
T9 |
1 |
|
T256 |
1 |
| others[2] |
168 |
1 |
|
T50 |
1 |
|
T9 |
1 |
|
T261 |
1 |
| others[3] |
312 |
1 |
|
T1 |
1 |
|
T46 |
1 |
|
T21 |
1 |
| false |
104 |
1 |
|
T203 |
1 |
|
T237 |
1 |
|
T123 |
4 |
| true |
4506 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
820 |
1 |
|
T312 |
1 |
|
T225 |
1 |
|
T370 |
1 |
| others[1] |
852 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| others[2] |
817 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| others[3] |
1367 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T275 |
1 |
| false |
434 |
1 |
|
T226 |
1 |
|
T294 |
1 |
|
T295 |
1 |
| true |
1157 |
1 |
|
T3 |
46 |
|
T19 |
1 |
|
T47 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
173 |
1 |
|
T140 |
1 |
|
T364 |
1 |
|
T322 |
1 |
| others[1] |
178 |
1 |
|
T203 |
1 |
|
T367 |
1 |
|
T123 |
12 |
| others[2] |
185 |
1 |
|
T17 |
1 |
|
T51 |
1 |
|
T20 |
1 |
| others[3] |
279 |
1 |
|
T1 |
1 |
|
T47 |
1 |
|
T50 |
1 |
| false |
89 |
1 |
|
T140 |
1 |
|
T368 |
1 |
|
T123 |
7 |
| true |
4543 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
162 |
1 |
|
T46 |
1 |
|
T20 |
1 |
|
T140 |
2 |
| others[1] |
153 |
1 |
|
T188 |
1 |
|
T9 |
1 |
|
T76 |
1 |
| others[2] |
179 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T34 |
1 |
| others[3] |
284 |
1 |
|
T9 |
2 |
|
T53 |
1 |
|
T35 |
1 |
| false |
87 |
1 |
|
T123 |
5 |
|
T372 |
1 |
|
T378 |
1 |
| true |
4582 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1028 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| others[1] |
963 |
1 |
|
T63 |
1 |
|
T224 |
1 |
|
T334 |
1 |
| others[2] |
955 |
1 |
|
T335 |
1 |
|
T370 |
1 |
|
T373 |
1 |
| others[3] |
1586 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| false |
545 |
1 |
|
T369 |
1 |
|
T3 |
12 |
|
T34 |
1 |
| true |
370 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
994 |
1 |
|
T63 |
1 |
|
T335 |
1 |
|
T226 |
1 |
| others[1] |
992 |
1 |
|
T224 |
1 |
|
T295 |
1 |
|
T370 |
1 |
| others[2] |
957 |
1 |
|
T64 |
1 |
|
T143 |
1 |
|
T230 |
1 |
| others[3] |
1661 |
1 |
|
T67 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| false |
497 |
1 |
|
T23 |
1 |
|
T334 |
1 |
|
T312 |
1 |
| true |
346 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
70 |
1 |
|
T359 |
1 |
|
T368 |
1 |
|
T237 |
1 |
| others[1] |
66 |
1 |
|
T17 |
1 |
|
T140 |
2 |
|
T123 |
3 |
| others[2] |
91 |
1 |
|
T34 |
2 |
|
T140 |
3 |
|
T363 |
1 |
| others[3] |
135 |
1 |
|
T4 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| false |
39 |
1 |
|
T140 |
1 |
|
T364 |
1 |
|
T123 |
1 |
| true |
5046 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
178 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T259 |
1 |
| others[1] |
188 |
1 |
|
T47 |
1 |
|
T34 |
1 |
|
T188 |
1 |
| others[2] |
178 |
1 |
|
T19 |
1 |
|
T50 |
1 |
|
T9 |
1 |
| others[3] |
288 |
1 |
|
T1 |
1 |
|
T21 |
1 |
|
T76 |
1 |
| false |
92 |
1 |
|
T4 |
1 |
|
T221 |
1 |
|
T359 |
1 |
| true |
4523 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
842 |
1 |
|
T23 |
1 |
|
T231 |
1 |
|
T225 |
1 |
| others[1] |
784 |
1 |
|
T67 |
1 |
|
T230 |
1 |
|
T312 |
1 |
| others[2] |
830 |
1 |
|
T64 |
1 |
|
T275 |
1 |
|
T335 |
1 |
| others[3] |
1398 |
1 |
|
T63 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| false |
417 |
1 |
|
T370 |
1 |
|
T369 |
1 |
|
T3 |
12 |
| true |
1176 |
1 |
|
T3 |
51 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
178 |
1 |
|
T17 |
1 |
|
T53 |
1 |
|
T35 |
1 |
| others[1] |
166 |
1 |
|
T20 |
1 |
|
T34 |
1 |
|
T118 |
1 |
| others[2] |
158 |
1 |
|
T120 |
1 |
|
T140 |
1 |
|
T359 |
1 |
| others[3] |
291 |
1 |
|
T50 |
1 |
|
T44 |
1 |
|
T21 |
1 |
| false |
88 |
1 |
|
T46 |
1 |
|
T123 |
6 |
|
T358 |
1 |
| true |
4566 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
154 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T140 |
1 |
| others[1] |
157 |
1 |
|
T140 |
2 |
|
T367 |
1 |
|
T123 |
7 |
| others[2] |
184 |
1 |
|
T9 |
2 |
|
T357 |
1 |
|
T140 |
1 |
| others[3] |
282 |
1 |
|
T34 |
1 |
|
T87 |
1 |
|
T140 |
1 |
| false |
85 |
1 |
|
T17 |
1 |
|
T9 |
1 |
|
T118 |
1 |
| true |
4585 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
961 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| others[1] |
977 |
1 |
|
T335 |
1 |
|
T226 |
1 |
|
T149 |
1 |
| others[2] |
982 |
1 |
|
T224 |
1 |
|
T334 |
1 |
|
T294 |
1 |
| others[3] |
1671 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| false |
494 |
1 |
|
T312 |
1 |
|
T148 |
1 |
|
T369 |
1 |
| true |
362 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
990 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T230 |
1 |
| others[1] |
941 |
1 |
|
T312 |
1 |
|
T226 |
1 |
|
T150 |
1 |
| others[2] |
1013 |
1 |
|
T63 |
1 |
|
T143 |
1 |
|
T275 |
1 |
| others[3] |
1659 |
1 |
|
T64 |
1 |
|
T144 |
1 |
|
T148 |
1 |
| false |
498 |
1 |
|
T224 |
1 |
|
T369 |
1 |
|
T366 |
1 |
| true |
346 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
77 |
1 |
|
T76 |
1 |
|
T140 |
1 |
|
T372 |
1 |
| others[1] |
75 |
1 |
|
T34 |
2 |
|
T188 |
1 |
|
T53 |
1 |
| others[2] |
68 |
1 |
|
T87 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| others[3] |
142 |
1 |
|
T361 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| false |
38 |
1 |
|
T140 |
1 |
|
T123 |
1 |
|
T73 |
4 |
| true |
5047 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
157 |
1 |
|
T9 |
2 |
|
T203 |
1 |
|
T261 |
1 |
| others[1] |
179 |
1 |
|
T17 |
1 |
|
T47 |
1 |
|
T50 |
1 |
| others[2] |
196 |
1 |
|
T4 |
1 |
|
T9 |
1 |
|
T120 |
1 |
| others[3] |
332 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T44 |
1 |
| false |
98 |
1 |
|
T1 |
1 |
|
T188 |
1 |
|
T121 |
1 |
| true |
4485 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
807 |
1 |
|
T144 |
1 |
|
T275 |
1 |
|
T148 |
1 |
| others[1] |
788 |
1 |
|
T67 |
1 |
|
T334 |
1 |
|
T3 |
11 |
| others[2] |
818 |
1 |
|
T230 |
1 |
|
T231 |
1 |
|
T312 |
1 |
| others[3] |
1439 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T143 |
1 |
| false |
428 |
1 |
|
T64 |
1 |
|
T294 |
1 |
|
T3 |
7 |
| true |
1167 |
1 |
|
T3 |
46 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
184 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T44 |
1 |
| others[1] |
198 |
1 |
|
T51 |
1 |
|
T188 |
1 |
|
T87 |
1 |
| others[2] |
159 |
1 |
|
T47 |
1 |
|
T76 |
1 |
|
T35 |
1 |
| others[3] |
273 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T189 |
1 |
| false |
96 |
1 |
|
T50 |
1 |
|
T21 |
1 |
|
T121 |
1 |
| true |
4537 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
163 |
1 |
|
T9 |
2 |
|
T35 |
1 |
|
T221 |
1 |
| others[1] |
164 |
1 |
|
T20 |
1 |
|
T9 |
1 |
|
T140 |
2 |
| others[2] |
180 |
1 |
|
T17 |
1 |
|
T9 |
1 |
|
T118 |
1 |
| others[3] |
288 |
1 |
|
T46 |
1 |
|
T47 |
1 |
|
T9 |
1 |
| false |
86 |
1 |
|
T9 |
1 |
|
T359 |
1 |
|
T123 |
3 |
| true |
4566 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
976 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| others[1] |
1042 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T231 |
1 |
| others[2] |
1014 |
1 |
|
T149 |
1 |
|
T3 |
23 |
|
T34 |
2 |
| others[3] |
1580 |
1 |
|
T67 |
1 |
|
T312 |
1 |
|
T148 |
1 |
| false |
476 |
1 |
|
T64 |
1 |
|
T3 |
9 |
|
T33 |
1 |
| true |
359 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
997 |
1 |
|
T64 |
1 |
|
T144 |
1 |
|
T224 |
1 |
| others[1] |
1009 |
1 |
|
T63 |
1 |
|
T143 |
1 |
|
T230 |
1 |
| others[2] |
985 |
1 |
|
T23 |
1 |
|
T334 |
1 |
|
T312 |
1 |
| others[3] |
1608 |
1 |
|
T275 |
1 |
|
T225 |
1 |
|
T148 |
1 |
| false |
509 |
1 |
|
T67 |
1 |
|
T226 |
1 |
|
T295 |
1 |
| true |
339 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
80 |
1 |
|
T34 |
1 |
|
T76 |
1 |
|
T140 |
1 |
| others[1] |
73 |
1 |
|
T140 |
1 |
|
T123 |
3 |
|
T358 |
1 |
| others[2] |
70 |
1 |
|
T140 |
2 |
|
T359 |
1 |
|
T123 |
4 |
| others[3] |
148 |
1 |
|
T17 |
1 |
|
T34 |
1 |
|
T35 |
1 |
| false |
31 |
1 |
|
T123 |
1 |
|
T371 |
1 |
|
T73 |
1 |
| true |
5045 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
185 |
1 |
|
T4 |
1 |
|
T116 |
1 |
|
T9 |
1 |
| others[1] |
191 |
1 |
|
T34 |
1 |
|
T84 |
1 |
|
T83 |
1 |
| others[2] |
185 |
1 |
|
T47 |
1 |
|
T34 |
1 |
|
T9 |
1 |
| others[3] |
326 |
1 |
|
T46 |
1 |
|
T51 |
1 |
|
T20 |
1 |
| false |
92 |
1 |
|
T7 |
1 |
|
T188 |
1 |
|
T9 |
1 |
| true |
4468 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |