Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
836 |
1 |
|
T67 |
1 |
|
T230 |
1 |
|
T370 |
1 |
| others[1] |
840 |
1 |
|
T23 |
1 |
|
T275 |
1 |
|
T292 |
1 |
| others[2] |
808 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T312 |
1 |
| others[3] |
1372 |
1 |
|
T143 |
1 |
|
T231 |
1 |
|
T224 |
1 |
| false |
436 |
1 |
|
T144 |
1 |
|
T334 |
1 |
|
T148 |
1 |
| true |
1155 |
1 |
|
T3 |
51 |
|
T4 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
183 |
1 |
|
T34 |
1 |
|
T123 |
17 |
|
T362 |
2 |
| others[1] |
173 |
1 |
|
T46 |
1 |
|
T20 |
1 |
|
T118 |
1 |
| others[2] |
180 |
1 |
|
T4 |
1 |
|
T21 |
1 |
|
T87 |
1 |
| others[3] |
291 |
1 |
|
T47 |
1 |
|
T76 |
1 |
|
T203 |
1 |
| false |
84 |
1 |
|
T256 |
1 |
|
T123 |
5 |
|
T371 |
1 |
| true |
4536 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
179 |
1 |
|
T20 |
1 |
|
T123 |
10 |
|
T376 |
1 |
| others[1] |
154 |
1 |
|
T357 |
1 |
|
T140 |
1 |
|
T123 |
10 |
| others[2] |
159 |
1 |
|
T9 |
2 |
|
T118 |
1 |
|
T140 |
1 |
| others[3] |
285 |
1 |
|
T34 |
1 |
|
T188 |
1 |
|
T9 |
2 |
| false |
80 |
1 |
|
T47 |
1 |
|
T140 |
1 |
|
T363 |
1 |
| true |
4590 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
971 |
1 |
|
T144 |
1 |
|
T231 |
1 |
|
T294 |
1 |
| others[1] |
963 |
1 |
|
T335 |
1 |
|
T281 |
1 |
|
T3 |
22 |
| others[2] |
1007 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T148 |
1 |
| others[3] |
1616 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T143 |
1 |
| false |
519 |
1 |
|
T334 |
1 |
|
T312 |
1 |
|
T226 |
1 |
| true |
371 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
978 |
1 |
|
T312 |
1 |
|
T289 |
1 |
|
T292 |
1 |
| others[1] |
979 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T67 |
1 |
| others[2] |
976 |
1 |
|
T143 |
1 |
|
T224 |
1 |
|
T334 |
1 |
| others[3] |
1662 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| false |
501 |
1 |
|
T64 |
1 |
|
T150 |
1 |
|
T3 |
10 |
| true |
351 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
65 |
1 |
|
T364 |
1 |
|
T123 |
7 |
|
T371 |
1 |
| others[1] |
65 |
1 |
|
T140 |
1 |
|
T363 |
1 |
|
T123 |
5 |
| others[2] |
87 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T53 |
1 |
| others[3] |
150 |
1 |
|
T34 |
1 |
|
T35 |
1 |
|
T140 |
2 |
| false |
35 |
1 |
|
T140 |
1 |
|
T123 |
1 |
|
T376 |
1 |
| true |
5045 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
185 |
1 |
|
T49 |
1 |
|
T188 |
1 |
|
T9 |
1 |
| others[1] |
197 |
1 |
|
T47 |
1 |
|
T50 |
1 |
|
T34 |
1 |
| others[2] |
173 |
1 |
|
T46 |
1 |
|
T51 |
1 |
|
T9 |
1 |
| others[3] |
292 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T53 |
1 |
| false |
86 |
1 |
|
T21 |
1 |
|
T123 |
5 |
|
T331 |
1 |
| true |
4514 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
832 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| others[1] |
803 |
1 |
|
T275 |
1 |
|
T335 |
1 |
|
T289 |
1 |
| others[2] |
873 |
1 |
|
T23 |
1 |
|
T143 |
1 |
|
T312 |
1 |
| others[3] |
1383 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T334 |
1 |
| false |
396 |
1 |
|
T3 |
5 |
|
T7 |
1 |
|
T8 |
1 |
| true |
1160 |
1 |
|
T1 |
1 |
|
T3 |
48 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
181 |
1 |
|
T44 |
1 |
|
T20 |
1 |
|
T140 |
3 |
| others[1] |
179 |
1 |
|
T46 |
1 |
|
T203 |
1 |
|
T363 |
1 |
| others[2] |
182 |
1 |
|
T34 |
1 |
|
T188 |
1 |
|
T118 |
1 |
| others[3] |
276 |
1 |
|
T17 |
1 |
|
T51 |
1 |
|
T140 |
1 |
| false |
99 |
1 |
|
T123 |
4 |
|
T332 |
1 |
|
T376 |
1 |
| true |
4530 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
152 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T76 |
1 |
| others[1] |
150 |
1 |
|
T9 |
1 |
|
T87 |
1 |
|
T361 |
1 |
| others[2] |
158 |
1 |
|
T46 |
1 |
|
T34 |
1 |
|
T140 |
1 |
| others[3] |
296 |
1 |
|
T9 |
2 |
|
T35 |
1 |
|
T357 |
1 |
| false |
81 |
1 |
|
T188 |
1 |
|
T189 |
1 |
|
T53 |
1 |
| true |
4610 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
996 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T231 |
1 |
| others[1] |
1016 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T230 |
1 |
| others[2] |
954 |
1 |
|
T63 |
1 |
|
T144 |
1 |
|
T224 |
1 |
| others[3] |
1573 |
1 |
|
T312 |
1 |
|
T335 |
1 |
|
T226 |
1 |
| false |
539 |
1 |
|
T370 |
1 |
|
T3 |
16 |
|
T168 |
1 |
| true |
369 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
960 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T230 |
1 |
| others[1] |
1015 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T143 |
1 |
| others[2] |
1020 |
1 |
|
T231 |
1 |
|
T334 |
1 |
|
T370 |
1 |
| others[3] |
1620 |
1 |
|
T275 |
1 |
|
T335 |
1 |
|
T294 |
1 |
| false |
487 |
1 |
|
T149 |
1 |
|
T373 |
1 |
|
T3 |
7 |
| true |
345 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
70 |
1 |
|
T35 |
1 |
|
T140 |
1 |
|
T123 |
1 |
| others[1] |
72 |
1 |
|
T140 |
2 |
|
T123 |
6 |
|
T362 |
1 |
| others[2] |
78 |
1 |
|
T34 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| others[3] |
140 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T140 |
3 |
| false |
33 |
1 |
|
T363 |
1 |
|
T367 |
1 |
|
T73 |
4 |
| true |
5054 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
181 |
1 |
|
T9 |
1 |
|
T121 |
1 |
|
T87 |
1 |
| others[1] |
162 |
1 |
|
T21 |
1 |
|
T9 |
1 |
|
T118 |
1 |
| others[2] |
180 |
1 |
|
T17 |
1 |
|
T34 |
2 |
|
T188 |
1 |
| others[3] |
314 |
1 |
|
T1 |
1 |
|
T44 |
1 |
|
T51 |
1 |
| false |
94 |
1 |
|
T123 |
7 |
|
T376 |
1 |
|
T372 |
1 |
| true |
4516 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
824 |
1 |
|
T67 |
1 |
|
T144 |
1 |
|
T292 |
1 |
| others[1] |
852 |
1 |
|
T312 |
1 |
|
T365 |
1 |
|
T281 |
1 |
| others[2] |
778 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T231 |
1 |
| others[3] |
1360 |
1 |
|
T230 |
1 |
|
T275 |
1 |
|
T224 |
1 |
| false |
420 |
1 |
|
T64 |
1 |
|
T143 |
1 |
|
T148 |
1 |
| true |
1213 |
1 |
|
T1 |
1 |
|
T3 |
55 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
183 |
1 |
|
T1 |
1 |
|
T34 |
2 |
|
T196 |
1 |
| others[1] |
166 |
1 |
|
T50 |
1 |
|
T51 |
1 |
|
T189 |
1 |
| others[2] |
175 |
1 |
|
T21 |
1 |
|
T140 |
1 |
|
T359 |
1 |
| others[3] |
264 |
1 |
|
T46 |
1 |
|
T7 |
1 |
|
T188 |
1 |
| false |
86 |
1 |
|
T4 |
1 |
|
T140 |
1 |
|
T123 |
5 |
| true |
4573 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
157 |
1 |
|
T53 |
1 |
|
T140 |
3 |
|
T221 |
1 |
| others[1] |
171 |
1 |
|
T140 |
1 |
|
T123 |
8 |
|
T362 |
1 |
| others[2] |
168 |
1 |
|
T9 |
2 |
|
T118 |
1 |
|
T87 |
1 |
| others[3] |
268 |
1 |
|
T46 |
1 |
|
T20 |
1 |
|
T34 |
1 |
| false |
85 |
1 |
|
T357 |
1 |
|
T123 |
6 |
|
T362 |
1 |
| true |
4598 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1013 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T334 |
1 |
| others[1] |
1015 |
1 |
|
T63 |
1 |
|
T312 |
1 |
|
T148 |
1 |
| others[2] |
990 |
1 |
|
T230 |
1 |
|
T275 |
1 |
|
T225 |
1 |
| others[3] |
1546 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| false |
516 |
1 |
|
T23 |
1 |
|
T3 |
10 |
|
T8 |
1 |
| true |
367 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
977 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| others[1] |
937 |
1 |
|
T143 |
1 |
|
T225 |
1 |
|
T150 |
1 |
| others[2] |
1041 |
1 |
|
T275 |
1 |
|
T335 |
1 |
|
T226 |
1 |
| others[3] |
1642 |
1 |
|
T23 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| false |
506 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T33 |
1 |
| true |
344 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
63 |
1 |
|
T357 |
1 |
|
T140 |
2 |
|
T123 |
4 |
| others[1] |
81 |
1 |
|
T4 |
1 |
|
T140 |
1 |
|
T363 |
1 |
| others[2] |
78 |
1 |
|
T34 |
2 |
|
T140 |
4 |
|
T367 |
1 |
| others[3] |
152 |
1 |
|
T17 |
1 |
|
T359 |
1 |
|
T364 |
1 |
| false |
33 |
1 |
|
T35 |
1 |
|
T140 |
1 |
|
T359 |
1 |
| true |
5040 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T7 |
1 |
|
T21 |
1 |
|
T121 |
1 |
| others[1] |
180 |
1 |
|
T20 |
1 |
|
T162 |
1 |
|
T35 |
1 |
| others[2] |
181 |
1 |
|
T84 |
1 |
|
T140 |
1 |
|
T261 |
1 |
| others[3] |
289 |
1 |
|
T4 |
1 |
|
T17 |
1 |
|
T47 |
1 |
| false |
72 |
1 |
|
T76 |
1 |
|
T123 |
4 |
|
T195 |
1 |
| true |
4521 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
790 |
1 |
|
T312 |
1 |
|
T226 |
1 |
|
T148 |
1 |
| others[1] |
833 |
1 |
|
T230 |
1 |
|
T3 |
8 |
|
T164 |
1 |
| others[2] |
769 |
1 |
|
T63 |
1 |
|
T144 |
1 |
|
T335 |
1 |
| others[3] |
1438 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T143 |
1 |
| false |
452 |
1 |
|
T67 |
1 |
|
T224 |
1 |
|
T366 |
1 |
| true |
1165 |
1 |
|
T3 |
55 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
166 |
1 |
|
T1 |
1 |
|
T188 |
1 |
|
T118 |
1 |
| others[1] |
181 |
1 |
|
T44 |
1 |
|
T51 |
1 |
|
T140 |
1 |
| others[2] |
178 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T162 |
1 |
| others[3] |
281 |
1 |
|
T47 |
1 |
|
T76 |
1 |
|
T53 |
1 |
| false |
94 |
1 |
|
T34 |
1 |
|
T203 |
1 |
|
T123 |
4 |
| true |
4547 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
159 |
1 |
|
T361 |
1 |
|
T140 |
2 |
|
T123 |
9 |
| others[1] |
165 |
1 |
|
T20 |
1 |
|
T34 |
1 |
|
T118 |
1 |
| others[2] |
161 |
1 |
|
T357 |
1 |
|
T140 |
1 |
|
T91 |
1 |
| others[3] |
302 |
1 |
|
T46 |
1 |
|
T188 |
1 |
|
T9 |
1 |
| false |
84 |
1 |
|
T221 |
1 |
|
T123 |
6 |
|
T376 |
1 |
| true |
4576 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
988 |
1 |
|
T335 |
1 |
|
T226 |
1 |
|
T370 |
1 |
| others[1] |
968 |
1 |
|
T144 |
1 |
|
T289 |
1 |
|
T365 |
1 |
| others[2] |
974 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T275 |
1 |
| others[3] |
1652 |
1 |
|
T23 |
1 |
|
T231 |
1 |
|
T334 |
1 |
| false |
508 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T230 |
1 |
| true |
357 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
956 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T224 |
1 |
| others[1] |
1062 |
1 |
|
T67 |
1 |
|
T231 |
1 |
|
T292 |
1 |
| others[2] |
977 |
1 |
|
T144 |
1 |
|
T275 |
1 |
|
T334 |
1 |
| others[3] |
1604 |
1 |
|
T64 |
1 |
|
T143 |
1 |
|
T230 |
1 |
| false |
501 |
1 |
|
T370 |
1 |
|
T3 |
8 |
|
T219 |
1 |
| true |
347 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
74 |
1 |
|
T140 |
2 |
|
T359 |
1 |
|
T123 |
3 |
| others[1] |
72 |
1 |
|
T34 |
1 |
|
T140 |
1 |
|
T367 |
1 |
| others[2] |
75 |
1 |
|
T34 |
1 |
|
T140 |
2 |
|
T123 |
3 |
| others[3] |
121 |
1 |
|
T140 |
2 |
|
T363 |
1 |
|
T368 |
1 |
| false |
38 |
1 |
|
T140 |
1 |
|
T359 |
1 |
|
T123 |
3 |
| true |
5067 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
170 |
1 |
|
T19 |
1 |
|
T51 |
1 |
|
T20 |
1 |
| others[1] |
176 |
1 |
|
T9 |
2 |
|
T189 |
1 |
|
T256 |
1 |
| others[2] |
161 |
1 |
|
T35 |
1 |
|
T140 |
2 |
|
T363 |
1 |
| others[3] |
321 |
1 |
|
T4 |
1 |
|
T9 |
2 |
|
T361 |
1 |
| false |
96 |
1 |
|
T188 |
1 |
|
T118 |
1 |
|
T162 |
1 |
| true |
4523 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
838 |
1 |
|
T23 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| others[1] |
830 |
1 |
|
T275 |
1 |
|
T312 |
1 |
|
T225 |
1 |
| others[2] |
823 |
1 |
|
T67 |
1 |
|
T335 |
1 |
|
T148 |
1 |
| others[3] |
1397 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T334 |
1 |
| false |
404 |
1 |
|
T143 |
1 |
|
T3 |
5 |
|
T177 |
1 |
| true |
1155 |
1 |
|
T3 |
45 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
160 |
1 |
|
T188 |
1 |
|
T196 |
1 |
|
T364 |
1 |
| others[1] |
178 |
1 |
|
T7 |
1 |
|
T21 |
1 |
|
T34 |
1 |
| others[2] |
165 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T87 |
1 |
| others[3] |
297 |
1 |
|
T50 |
1 |
|
T44 |
1 |
|
T20 |
1 |
| false |
90 |
1 |
|
T47 |
1 |
|
T51 |
1 |
|
T140 |
1 |
| true |
4557 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
172 |
1 |
|
T9 |
1 |
|
T140 |
1 |
|
T123 |
11 |
| others[1] |
169 |
1 |
|
T46 |
1 |
|
T34 |
1 |
|
T9 |
1 |
| others[2] |
157 |
1 |
|
T34 |
1 |
|
T9 |
1 |
|
T140 |
1 |
| others[3] |
277 |
1 |
|
T4 |
1 |
|
T47 |
1 |
|
T20 |
1 |
| false |
67 |
1 |
|
T140 |
1 |
|
T123 |
4 |
|
T73 |
5 |
| true |
4605 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |