Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
973 |
1 |
|
T23 |
1 |
|
T143 |
1 |
|
T230 |
1 |
| others[1] |
962 |
1 |
|
T64 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| others[2] |
988 |
1 |
|
T292 |
1 |
|
T370 |
1 |
|
T366 |
1 |
| others[3] |
1612 |
1 |
|
T63 |
1 |
|
T312 |
1 |
|
T225 |
1 |
| false |
534 |
1 |
|
T67 |
1 |
|
T275 |
1 |
|
T224 |
1 |
| true |
378 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
960 |
1 |
|
T67 |
1 |
|
T230 |
1 |
|
T312 |
1 |
| others[1] |
1017 |
1 |
|
T231 |
1 |
|
T334 |
1 |
|
T292 |
1 |
| others[2] |
936 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T144 |
1 |
| others[3] |
1688 |
1 |
|
T143 |
1 |
|
T225 |
1 |
|
T289 |
1 |
| false |
500 |
1 |
|
T63 |
1 |
|
T295 |
1 |
|
T3 |
8 |
| true |
346 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
57 |
1 |
|
T140 |
2 |
|
T359 |
1 |
|
T364 |
1 |
| others[1] |
86 |
1 |
|
T140 |
1 |
|
T123 |
4 |
|
T137 |
1 |
| others[2] |
77 |
1 |
|
T140 |
1 |
|
T123 |
2 |
|
T374 |
1 |
| others[3] |
130 |
1 |
|
T34 |
1 |
|
T357 |
1 |
|
T140 |
2 |
| false |
46 |
1 |
|
T34 |
1 |
|
T140 |
2 |
|
T359 |
1 |
| true |
5051 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
168 |
1 |
|
T17 |
1 |
|
T49 |
1 |
|
T44 |
1 |
| others[1] |
196 |
1 |
|
T9 |
1 |
|
T140 |
1 |
|
T259 |
1 |
| others[2] |
191 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T162 |
1 |
| others[3] |
281 |
1 |
|
T9 |
2 |
|
T117 |
1 |
|
T256 |
1 |
| false |
99 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T50 |
1 |
| true |
4512 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
777 |
1 |
|
T67 |
1 |
|
T289 |
1 |
|
T149 |
1 |
| others[1] |
846 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T366 |
1 |
| others[2] |
841 |
1 |
|
T148 |
1 |
|
T365 |
1 |
|
T3 |
6 |
| others[3] |
1351 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T143 |
1 |
| false |
441 |
1 |
|
T64 |
1 |
|
T275 |
1 |
|
T334 |
1 |
| true |
1191 |
1 |
|
T3 |
52 |
|
T7 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
172 |
1 |
|
T140 |
2 |
|
T359 |
1 |
|
T259 |
1 |
| others[1] |
172 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T121 |
1 |
| others[2] |
162 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T203 |
1 |
| others[3] |
315 |
1 |
|
T47 |
1 |
|
T51 |
1 |
|
T21 |
1 |
| false |
95 |
1 |
|
T1 |
1 |
|
T87 |
1 |
|
T123 |
8 |
| true |
4531 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
184 |
1 |
|
T140 |
1 |
|
T91 |
1 |
|
T123 |
9 |
| others[1] |
164 |
1 |
|
T9 |
3 |
|
T35 |
1 |
|
T361 |
1 |
| others[2] |
168 |
1 |
|
T118 |
1 |
|
T123 |
16 |
|
T362 |
1 |
| others[3] |
257 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T9 |
1 |
| false |
82 |
1 |
|
T9 |
1 |
|
T123 |
4 |
|
T378 |
1 |
| true |
4592 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
979 |
1 |
|
T143 |
1 |
|
T224 |
1 |
|
T226 |
1 |
| others[1] |
996 |
1 |
|
T67 |
1 |
|
T370 |
1 |
|
T3 |
28 |
| others[2] |
1016 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| others[3] |
1576 |
1 |
|
T230 |
1 |
|
T334 |
1 |
|
T312 |
1 |
| false |
512 |
1 |
|
T231 |
1 |
|
T373 |
1 |
|
T150 |
1 |
| true |
368 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
974 |
1 |
|
T312 |
1 |
|
T148 |
1 |
|
T370 |
1 |
| others[1] |
1005 |
1 |
|
T144 |
1 |
|
T275 |
1 |
|
T225 |
1 |
| others[2] |
1017 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T143 |
1 |
| others[3] |
1593 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T224 |
1 |
| false |
512 |
1 |
|
T335 |
1 |
|
T3 |
17 |
|
T33 |
2 |
| true |
346 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
80 |
1 |
|
T34 |
1 |
|
T140 |
3 |
|
T359 |
1 |
| others[1] |
101 |
1 |
|
T140 |
1 |
|
T359 |
1 |
|
T123 |
2 |
| others[2] |
85 |
1 |
|
T34 |
1 |
|
T140 |
2 |
|
T363 |
1 |
| others[3] |
125 |
1 |
|
T76 |
1 |
|
T140 |
2 |
|
T367 |
1 |
| false |
36 |
1 |
|
T123 |
3 |
|
T376 |
2 |
|
T375 |
1 |
| true |
5020 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
194 |
1 |
|
T20 |
1 |
|
T118 |
1 |
|
T357 |
1 |
| others[1] |
171 |
1 |
|
T34 |
1 |
|
T9 |
1 |
|
T91 |
1 |
| others[2] |
182 |
1 |
|
T17 |
1 |
|
T188 |
1 |
|
T116 |
1 |
| others[3] |
297 |
1 |
|
T7 |
1 |
|
T50 |
1 |
|
T34 |
1 |
| false |
88 |
1 |
|
T44 |
1 |
|
T361 |
1 |
|
T140 |
2 |
| true |
4515 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
838 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T144 |
1 |
| others[1] |
807 |
1 |
|
T143 |
1 |
|
T335 |
1 |
|
T292 |
1 |
| others[2] |
836 |
1 |
|
T230 |
1 |
|
T225 |
1 |
|
T281 |
1 |
| others[3] |
1380 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T224 |
1 |
| false |
425 |
1 |
|
T294 |
1 |
|
T3 |
3 |
|
T33 |
1 |
| true |
1161 |
1 |
|
T1 |
1 |
|
T3 |
44 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
169 |
1 |
|
T51 |
1 |
|
T34 |
1 |
|
T140 |
1 |
| others[1] |
184 |
1 |
|
T46 |
1 |
|
T53 |
1 |
|
T140 |
1 |
| others[2] |
191 |
1 |
|
T47 |
1 |
|
T259 |
1 |
|
T261 |
1 |
| others[3] |
270 |
1 |
|
T21 |
1 |
|
T189 |
1 |
|
T162 |
1 |
| false |
95 |
1 |
|
T188 |
1 |
|
T118 |
1 |
|
T140 |
1 |
| true |
4538 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
164 |
1 |
|
T188 |
1 |
|
T9 |
2 |
|
T140 |
1 |
| others[1] |
149 |
1 |
|
T34 |
1 |
|
T9 |
1 |
|
T118 |
1 |
| others[2] |
170 |
1 |
|
T17 |
1 |
|
T53 |
1 |
|
T140 |
1 |
| others[3] |
278 |
1 |
|
T46 |
1 |
|
T47 |
1 |
|
T20 |
1 |
| false |
90 |
1 |
|
T140 |
3 |
|
T123 |
5 |
|
T376 |
1 |
| true |
4596 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1006 |
1 |
|
T143 |
1 |
|
T225 |
1 |
|
T370 |
1 |
| others[1] |
948 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T144 |
1 |
| others[2] |
980 |
1 |
|
T334 |
1 |
|
T289 |
1 |
|
T373 |
1 |
| others[3] |
1594 |
1 |
|
T63 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| false |
545 |
1 |
|
T23 |
1 |
|
T3 |
9 |
|
T71 |
1 |
| true |
374 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
944 |
1 |
|
T231 |
1 |
|
T224 |
1 |
|
T312 |
1 |
| others[1] |
1012 |
1 |
|
T144 |
1 |
|
T275 |
1 |
|
T226 |
1 |
| others[2] |
1001 |
1 |
|
T64 |
1 |
|
T143 |
1 |
|
T334 |
1 |
| others[3] |
1655 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T225 |
1 |
| false |
486 |
1 |
|
T67 |
1 |
|
T230 |
1 |
|
T295 |
1 |
| true |
349 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
84 |
1 |
|
T140 |
3 |
|
T359 |
1 |
|
T363 |
1 |
| others[1] |
73 |
1 |
|
T140 |
1 |
|
T368 |
1 |
|
T237 |
1 |
| others[2] |
72 |
1 |
|
T140 |
1 |
|
T123 |
5 |
|
T372 |
2 |
| others[3] |
123 |
1 |
|
T34 |
2 |
|
T53 |
1 |
|
T140 |
1 |
| false |
41 |
1 |
|
T140 |
2 |
|
T123 |
6 |
|
T73 |
3 |
| true |
5054 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
184 |
1 |
|
T9 |
1 |
|
T117 |
1 |
|
T140 |
1 |
| others[1] |
168 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T47 |
1 |
| others[2] |
166 |
1 |
|
T7 |
1 |
|
T188 |
1 |
|
T361 |
1 |
| others[3] |
317 |
1 |
|
T21 |
1 |
|
T9 |
1 |
|
T357 |
1 |
| false |
84 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T118 |
1 |
| true |
4528 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
795 |
1 |
|
T23 |
1 |
|
T230 |
1 |
|
T226 |
1 |
| others[1] |
788 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| others[2] |
851 |
1 |
|
T275 |
1 |
|
T334 |
1 |
|
T312 |
1 |
| others[3] |
1401 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T224 |
1 |
| false |
411 |
1 |
|
T295 |
1 |
|
T365 |
1 |
|
T3 |
3 |
| true |
1201 |
1 |
|
T1 |
1 |
|
T3 |
58 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
170 |
1 |
|
T118 |
1 |
|
T162 |
1 |
|
T256 |
1 |
| others[1] |
197 |
1 |
|
T1 |
1 |
|
T357 |
1 |
|
T140 |
1 |
| others[2] |
194 |
1 |
|
T34 |
1 |
|
T189 |
1 |
|
T53 |
1 |
| others[3] |
304 |
1 |
|
T17 |
1 |
|
T34 |
1 |
|
T188 |
1 |
| false |
80 |
1 |
|
T47 |
1 |
|
T50 |
1 |
|
T140 |
1 |
| true |
4502 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
165 |
1 |
|
T4 |
1 |
|
T35 |
1 |
|
T87 |
1 |
| others[1] |
156 |
1 |
|
T9 |
1 |
|
T140 |
2 |
|
T221 |
1 |
| others[2] |
184 |
1 |
|
T140 |
2 |
|
T123 |
10 |
|
T376 |
2 |
| others[3] |
293 |
1 |
|
T20 |
1 |
|
T34 |
1 |
|
T188 |
1 |
| false |
80 |
1 |
|
T189 |
1 |
|
T367 |
1 |
|
T123 |
4 |
| true |
4569 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1008 |
1 |
|
T63 |
1 |
|
T144 |
1 |
|
T334 |
1 |
| others[1] |
949 |
1 |
|
T64 |
1 |
|
T275 |
1 |
|
T292 |
1 |
| others[2] |
1009 |
1 |
|
T143 |
1 |
|
T226 |
1 |
|
T149 |
1 |
| others[3] |
1619 |
1 |
|
T67 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| false |
499 |
1 |
|
T23 |
1 |
|
T289 |
1 |
|
T365 |
1 |
| true |
363 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T231 |
1 |
| others[1] |
965 |
1 |
|
T225 |
1 |
|
T373 |
1 |
|
T3 |
21 |
| others[2] |
983 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T275 |
1 |
| others[3] |
1583 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T230 |
1 |
| false |
558 |
1 |
|
T224 |
1 |
|
T334 |
1 |
|
T289 |
1 |
| true |
342 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
86 |
1 |
|
T34 |
2 |
|
T140 |
2 |
|
T123 |
6 |
| others[1] |
66 |
1 |
|
T46 |
1 |
|
T35 |
1 |
|
T357 |
1 |
| others[2] |
91 |
1 |
|
T53 |
1 |
|
T140 |
2 |
|
T363 |
1 |
| others[3] |
149 |
1 |
|
T140 |
3 |
|
T359 |
1 |
|
T123 |
10 |
| false |
47 |
1 |
|
T140 |
1 |
|
T359 |
1 |
|
T237 |
1 |
| true |
5008 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
163 |
1 |
|
T117 |
1 |
|
T256 |
1 |
|
T140 |
1 |
| others[1] |
192 |
1 |
|
T50 |
1 |
|
T44 |
1 |
|
T20 |
1 |
| others[2] |
175 |
1 |
|
T46 |
1 |
|
T47 |
1 |
|
T34 |
1 |
| others[3] |
297 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| false |
90 |
1 |
|
T49 |
1 |
|
T9 |
1 |
|
T123 |
8 |
| true |
4530 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
797 |
1 |
|
T64 |
1 |
|
T231 |
1 |
|
T275 |
1 |
| others[1] |
821 |
1 |
|
T67 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| others[2] |
825 |
1 |
|
T143 |
1 |
|
T335 |
1 |
|
T292 |
1 |
| others[3] |
1395 |
1 |
|
T63 |
1 |
|
T148 |
1 |
|
T295 |
1 |
| false |
434 |
1 |
|
T23 |
1 |
|
T312 |
1 |
|
T294 |
1 |
| true |
1175 |
1 |
|
T1 |
1 |
|
T3 |
48 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
189 |
1 |
|
T20 |
1 |
|
T21 |
1 |
|
T162 |
1 |
| others[1] |
162 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T35 |
1 |
| others[2] |
169 |
1 |
|
T7 |
1 |
|
T256 |
1 |
|
T140 |
2 |
| others[3] |
267 |
1 |
|
T44 |
1 |
|
T118 |
1 |
|
T189 |
1 |
| false |
98 |
1 |
|
T196 |
1 |
|
T140 |
1 |
|
T259 |
1 |
| true |
4562 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
157 |
1 |
|
T47 |
1 |
|
T9 |
2 |
|
T53 |
1 |
| others[1] |
164 |
1 |
|
T123 |
11 |
|
T376 |
2 |
|
T81 |
1 |
| others[2] |
171 |
1 |
|
T9 |
2 |
|
T189 |
1 |
|
T363 |
1 |
| others[3] |
286 |
1 |
|
T20 |
1 |
|
T140 |
1 |
|
T367 |
1 |
| false |
79 |
1 |
|
T34 |
1 |
|
T140 |
1 |
|
T123 |
6 |
| true |
4590 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1045 |
1 |
|
T63 |
1 |
|
T230 |
1 |
|
T225 |
1 |
| others[1] |
972 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T334 |
1 |
| others[2] |
949 |
1 |
|
T64 |
1 |
|
T224 |
1 |
|
T312 |
1 |
| others[3] |
1628 |
1 |
|
T23 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| false |
487 |
1 |
|
T3 |
6 |
|
T71 |
1 |
|
T219 |
1 |
| true |
366 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T11 |
1 |
|
T379 |
1 |
|
T380 |
1 |
| others[1] |
11 |
1 |
|
T95 |
1 |
|
T96 |
1 |
|
T36 |
1 |
| others[2] |
4 |
1 |
|
T94 |
1 |
|
T381 |
1 |
|
T382 |
1 |
| others[3] |
7 |
1 |
|
T24 |
1 |
|
T383 |
1 |
|
T180 |
1 |
| false |
3 |
1 |
|
T384 |
1 |
|
T385 |
1 |
|
T386 |
1 |
| true |
44 |
1 |
|
T2 |
1 |
|
T93 |
1 |
|
T154 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T32 |
1 |
|
T387 |
1 |
|
- |
- |
| others[1] |
1 |
1 |
|
T5 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
3 |
1 |
|
T283 |
1 |
|
T351 |
1 |
|
T353 |
1 |
| others[3] |
4 |
1 |
|
T37 |
1 |
|
T388 |
1 |
|
T389 |
1 |
| false |
7 |
1 |
|
T344 |
1 |
|
T390 |
1 |
|
T354 |
1 |
| true |
22 |
1 |
|
T391 |
1 |
|
T356 |
1 |
|
T135 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |