Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8688 |
1 |
|
T275 |
1 |
|
T148 |
1 |
|
T289 |
1 |
| others[1] |
387 |
1 |
|
T144 |
1 |
|
T47 |
1 |
|
T33 |
2 |
| others[2] |
367 |
1 |
|
T225 |
1 |
|
T365 |
1 |
|
T19 |
1 |
| others[3] |
577 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T143 |
1 |
| false |
175 |
1 |
|
T226 |
1 |
|
T292 |
1 |
|
T72 |
1 |
| true |
1689 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T230 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8534 |
1 |
|
T63 |
1 |
|
T144 |
1 |
|
T231 |
1 |
| others[1] |
202 |
1 |
|
T67 |
1 |
|
T370 |
1 |
|
T46 |
1 |
| others[2] |
202 |
1 |
|
T143 |
1 |
|
T289 |
1 |
|
T4 |
1 |
| others[3] |
331 |
1 |
|
T23 |
1 |
|
T312 |
1 |
|
T295 |
1 |
| false |
93 |
1 |
|
T230 |
1 |
|
T188 |
1 |
|
T140 |
1 |
| true |
2521 |
1 |
|
T64 |
1 |
|
T275 |
1 |
|
T224 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8511 |
1 |
|
T292 |
1 |
|
T294 |
1 |
|
T373 |
1 |
| others[1] |
183 |
1 |
|
T23 |
1 |
|
T289 |
1 |
|
T4 |
1 |
| others[2] |
209 |
1 |
|
T230 |
1 |
|
T224 |
1 |
|
T334 |
1 |
| others[3] |
310 |
1 |
|
T144 |
1 |
|
T335 |
1 |
|
T365 |
1 |
| false |
87 |
1 |
|
T231 |
1 |
|
T149 |
1 |
|
T33 |
1 |
| true |
2583 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8935 |
1 |
|
T312 |
1 |
|
T150 |
1 |
|
T3 |
100 |
| others[1] |
625 |
1 |
|
T148 |
1 |
|
T373 |
1 |
|
T281 |
1 |
| others[2] |
637 |
1 |
|
T275 |
1 |
|
T334 |
1 |
|
T335 |
1 |
| others[3] |
966 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
| false |
331 |
1 |
|
T226 |
1 |
|
T370 |
1 |
|
T52 |
1 |
| true |
389 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8943 |
1 |
|
T230 |
1 |
|
T275 |
1 |
|
T312 |
1 |
| others[1] |
631 |
1 |
|
T225 |
1 |
|
T335 |
1 |
|
T148 |
1 |
| others[2] |
602 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T143 |
1 |
| others[3] |
1011 |
1 |
|
T23 |
1 |
|
T67 |
1 |
|
T224 |
1 |
| false |
286 |
1 |
|
T144 |
1 |
|
T289 |
1 |
|
T294 |
1 |
| true |
410 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2074 |
1 |
|
T143 |
1 |
|
T225 |
1 |
|
T365 |
1 |
| others[1] |
2137 |
1 |
|
T226 |
1 |
|
T289 |
1 |
|
T292 |
1 |
| others[2] |
2031 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T231 |
1 |
| others[3] |
3374 |
1 |
|
T63 |
1 |
|
T144 |
1 |
|
T230 |
1 |
| false |
1034 |
1 |
|
T67 |
1 |
|
T294 |
1 |
|
T369 |
1 |
| true |
1233 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8509 |
1 |
|
T275 |
1 |
|
T289 |
1 |
|
T281 |
1 |
| others[1] |
206 |
1 |
|
T231 |
1 |
|
T226 |
1 |
|
T148 |
1 |
| others[2] |
212 |
1 |
|
T150 |
1 |
|
T17 |
1 |
|
T8 |
1 |
| others[3] |
362 |
1 |
|
T67 |
1 |
|
T144 |
1 |
|
T225 |
1 |
| false |
113 |
1 |
|
T366 |
1 |
|
T1 |
1 |
|
T4 |
1 |
| true |
2481 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8676 |
1 |
|
T64 |
1 |
|
T143 |
1 |
|
T230 |
1 |
| others[1] |
345 |
1 |
|
T312 |
1 |
|
T335 |
1 |
|
T369 |
1 |
| others[2] |
387 |
1 |
|
T295 |
1 |
|
T370 |
1 |
|
T4 |
1 |
| others[3] |
613 |
1 |
|
T23 |
1 |
|
T294 |
1 |
|
T281 |
1 |
| false |
189 |
1 |
|
T33 |
1 |
|
T193 |
5 |
|
T55 |
1 |
| true |
1673 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T144 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8526 |
1 |
|
T275 |
1 |
|
T150 |
1 |
|
T3 |
100 |
| others[1] |
206 |
1 |
|
T225 |
1 |
|
T226 |
1 |
|
T47 |
1 |
| others[2] |
180 |
1 |
|
T295 |
1 |
|
T370 |
1 |
|
T15 |
1 |
| others[3] |
331 |
1 |
|
T312 |
1 |
|
T148 |
1 |
|
T289 |
1 |
| false |
119 |
1 |
|
T231 |
1 |
|
T335 |
1 |
|
T292 |
1 |
| true |
2521 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8506 |
1 |
|
T334 |
1 |
|
T150 |
1 |
|
T3 |
100 |
| others[1] |
171 |
1 |
|
T231 |
1 |
|
T225 |
1 |
|
T20 |
1 |
| others[2] |
186 |
1 |
|
T144 |
1 |
|
T292 |
1 |
|
T366 |
1 |
| others[3] |
324 |
1 |
|
T148 |
1 |
|
T294 |
1 |
|
T149 |
1 |
| false |
112 |
1 |
|
T275 |
1 |
|
T224 |
1 |
|
T289 |
1 |
| true |
2584 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8998 |
1 |
|
T23 |
1 |
|
T275 |
1 |
|
T312 |
1 |
| others[1] |
624 |
1 |
|
T144 |
1 |
|
T224 |
1 |
|
T289 |
1 |
| others[2] |
592 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T335 |
1 |
| others[3] |
986 |
1 |
|
T230 |
1 |
|
T231 |
1 |
|
T334 |
1 |
| false |
289 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T15 |
1 |
| true |
394 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8917 |
1 |
|
T334 |
1 |
|
T312 |
1 |
|
T370 |
1 |
| others[1] |
600 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T230 |
1 |
| others[2] |
640 |
1 |
|
T144 |
1 |
|
T231 |
1 |
|
T275 |
1 |
| others[3] |
992 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T143 |
1 |
| false |
311 |
1 |
|
T335 |
1 |
|
T289 |
1 |
|
T292 |
1 |
| true |
423 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2084 |
1 |
|
T230 |
1 |
|
T231 |
1 |
|
T294 |
1 |
| others[1] |
2098 |
1 |
|
T289 |
1 |
|
T149 |
1 |
|
T3 |
16 |
| others[2] |
2042 |
1 |
|
T312 |
1 |
|
T370 |
1 |
|
T365 |
1 |
| others[3] |
3415 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T143 |
1 |
| false |
1044 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T144 |
1 |
| true |
1200 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8544 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T295 |
1 |
| others[1] |
219 |
1 |
|
T275 |
1 |
|
T294 |
1 |
|
T17 |
1 |
| others[2] |
217 |
1 |
|
T67 |
1 |
|
T150 |
1 |
|
T44 |
1 |
| others[3] |
358 |
1 |
|
T312 |
1 |
|
T225 |
1 |
|
T226 |
1 |
| false |
125 |
1 |
|
T373 |
1 |
|
T34 |
1 |
|
T188 |
1 |
| true |
2420 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T64 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8695 |
1 |
|
T144 |
1 |
|
T275 |
1 |
|
T148 |
1 |
| others[1] |
367 |
1 |
|
T23 |
1 |
|
T312 |
1 |
|
T295 |
1 |
| others[2] |
395 |
1 |
|
T224 |
1 |
|
T292 |
1 |
|
T294 |
1 |
| others[3] |
563 |
1 |
|
T64 |
1 |
|
T230 |
1 |
|
T225 |
1 |
| false |
197 |
1 |
|
T67 |
1 |
|
T149 |
1 |
|
T373 |
1 |
| true |
1666 |
1 |
|
T63 |
1 |
|
T143 |
1 |
|
T231 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8507 |
1 |
|
T143 |
1 |
|
T275 |
1 |
|
T335 |
1 |
| others[1] |
222 |
1 |
|
T144 |
1 |
|
T294 |
1 |
|
T370 |
1 |
| others[2] |
186 |
1 |
|
T225 |
1 |
|
T289 |
1 |
|
T118 |
1 |
| others[3] |
316 |
1 |
|
T23 |
1 |
|
T149 |
1 |
|
T150 |
1 |
| false |
101 |
1 |
|
T8 |
1 |
|
T368 |
1 |
|
T237 |
1 |
| true |
2551 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8516 |
1 |
|
T23 |
1 |
|
T230 |
1 |
|
T3 |
100 |
| others[1] |
196 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T294 |
1 |
| others[2] |
204 |
1 |
|
T312 |
1 |
|
T225 |
1 |
|
T17 |
1 |
| others[3] |
319 |
1 |
|
T63 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| false |
95 |
1 |
|
T4 |
1 |
|
T33 |
1 |
|
T9 |
1 |
| true |
2553 |
1 |
|
T231 |
1 |
|
T275 |
1 |
|
T224 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8918 |
1 |
|
T335 |
1 |
|
T365 |
1 |
|
T149 |
1 |
| others[1] |
587 |
1 |
|
T23 |
1 |
|
T144 |
1 |
|
T225 |
1 |
| others[2] |
664 |
1 |
|
T143 |
1 |
|
T230 |
1 |
|
T231 |
1 |
| others[3] |
981 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T67 |
1 |
| false |
337 |
1 |
|
T334 |
1 |
|
T292 |
1 |
|
T33 |
1 |
| true |
396 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8910 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T144 |
1 |
| others[1] |
593 |
1 |
|
T23 |
1 |
|
T224 |
1 |
|
T225 |
1 |
| others[2] |
649 |
1 |
|
T312 |
1 |
|
T226 |
1 |
|
T365 |
1 |
| others[3] |
1013 |
1 |
|
T67 |
1 |
|
T143 |
1 |
|
T231 |
1 |
| false |
289 |
1 |
|
T334 |
1 |
|
T52 |
1 |
|
T193 |
11 |
| true |
429 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2073 |
1 |
|
T335 |
1 |
|
T148 |
1 |
|
T295 |
1 |
| others[1] |
2130 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T224 |
1 |
| others[2] |
2063 |
1 |
|
T144 |
1 |
|
T230 |
1 |
|
T226 |
1 |
| others[3] |
3334 |
1 |
|
T23 |
1 |
|
T64 |
1 |
|
T143 |
1 |
| false |
1045 |
1 |
|
T231 |
1 |
|
T292 |
1 |
|
T294 |
1 |
| true |
1238 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8532 |
1 |
|
T67 |
1 |
|
T3 |
100 |
|
T40 |
205 |
| others[1] |
207 |
1 |
|
T292 |
1 |
|
T21 |
1 |
|
T33 |
1 |
| others[2] |
194 |
1 |
|
T335 |
1 |
|
T365 |
1 |
|
T366 |
1 |
| others[3] |
336 |
1 |
|
T23 |
1 |
|
T148 |
1 |
|
T289 |
1 |
| false |
104 |
1 |
|
T275 |
1 |
|
T312 |
1 |
|
T373 |
1 |
| true |
2510 |
1 |
|
T63 |
1 |
|
T64 |
1 |
|
T143 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8665 |
1 |
|
T231 |
1 |
|
T3 |
100 |
|
T15 |
1 |
| others[1] |
362 |
1 |
|
T64 |
1 |
|
T230 |
1 |
|
T312 |
1 |
| others[2] |
338 |
1 |
|
T23 |
1 |
|
T224 |
1 |
|
T226 |
1 |
| others[3] |
610 |
1 |
|
T275 |
1 |
|
T148 |
1 |
|
T289 |
1 |
| false |
176 |
1 |
|
T366 |
1 |
|
T9 |
1 |
|
T52 |
1 |
| true |
1732 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T143 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8527 |
1 |
|
T23 |
1 |
|
T334 |
1 |
|
T369 |
1 |
| others[1] |
184 |
1 |
|
T63 |
1 |
|
T335 |
1 |
|
T150 |
1 |
| others[2] |
212 |
1 |
|
T33 |
1 |
|
T118 |
1 |
|
T85 |
1 |
| others[3] |
339 |
1 |
|
T143 |
1 |
|
T289 |
1 |
|
T295 |
1 |
| false |
110 |
1 |
|
T373 |
1 |
|
T281 |
1 |
|
T363 |
1 |
| true |
2511 |
1 |
|
T64 |
1 |
|
T67 |
1 |
|
T144 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8512 |
1 |
|
T23 |
1 |
|
T335 |
1 |
|
T289 |
1 |
| others[1] |
187 |
1 |
|
T224 |
1 |
|
T334 |
1 |
|
T226 |
1 |
| others[2] |
176 |
1 |
|
T64 |
1 |
|
T17 |
1 |
|
T33 |
1 |
| others[3] |
298 |
1 |
|
T312 |
1 |
|
T150 |
1 |
|
T46 |
1 |
| false |
105 |
1 |
|
T292 |
1 |
|
T149 |
1 |
|
T47 |
1 |
| true |
2605 |
1 |
|
T63 |
1 |
|
T67 |
1 |
|
T143 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8957 |
1 |
|
T226 |
1 |
|
T294 |
1 |
|
T3 |
100 |
| others[1] |
605 |
1 |
|
T64 |
1 |
|
T312 |
1 |
|
T335 |
1 |
| others[2] |
591 |
1 |
|
T144 |
1 |
|
T275 |
1 |
|
T295 |
1 |
| others[3] |
1035 |
1 |
|
T23 |
1 |
|
T63 |
1 |
|
T67 |
1 |
| false |
310 |
1 |
|
T370 |
1 |
|
T219 |
1 |
|
T33 |
1 |
| true |
385 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |