Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	187519	1		T1	51		T3	600		T4	1359
auto[FlashEraseBank]	171022	1		T1	21		T4	1253		T17	55

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	201535	1		T1	41		T3	200		T4	1363
auto[FlashOpProgram]	139994	1		T3	100		T4	1249		T5	192
auto[FlashOpErase]	13612	1		T1	31		T3	100		T5	12
auto[FlashOpInvalid]	3400	1		T3	200		T122	200		T207	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	201535	1		T1	41		T3	200		T4	1363
op[FlashOpProgram]	139994	1		T3	100		T4	1249		T5	192
op[FlashOpErase]	13612	1		T1	31		T3	100		T5	12
read_erase_read	599	1		T1	27		T5	1		T50	32
read_prog_read	963	1		T4	6		T19	6		T49	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	244479	1		T1	14		T3	558		T4	1999
auto[FlashPartInfo]	111061	1		T1	57		T3	30		T4	594
auto[FlashPartInfo1]	621	1		T4	4		T20	5		T33	10
auto[FlashPartInfo2]	2380	1		T1	1		T3	12		T4	15

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	149025	1		T1	7		T3	186		T4	1051
auto[FlashPartData]	auto[FlashOpProgram]	89046	1		T3	93		T4	948		T17	173
auto[FlashPartData]	auto[FlashOpErase]	3094	1		T1	7		T3	93		T50	11
auto[FlashPartData]	auto[FlashOpInvalid]	3314	1		T3	186		T122	186		T207	194
auto[FlashPartInfo]	auto[FlashOpRead]	50528	1		T1	33		T3	10		T4	297
auto[FlashPartInfo]	auto[FlashOpProgram]	49993	1		T3	5		T4	297		T5	192
auto[FlashPartInfo]	auto[FlashOpErase]	10472	1		T1	24		T3	5		T5	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T3	10		T122	10		T207	2
auto[FlashPartInfo1]	auto[FlashOpRead]	547	1		T4	4		T20	5		T33	10
auto[FlashPartInfo1]	auto[FlashOpProgram]	67	1		T75	1		T105	32		T127	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T75	1		T127	1		T107	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T75	2		T127	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1435	1		T1	1		T3	4		T4	11
auto[FlashPartInfo2]	auto[FlashOpProgram]	888	1		T3	2		T4	4		T19	2
auto[FlashPartInfo2]	auto[FlashOpErase]	43	1		T3	2		T50	17		T122	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T3	4		T122	4		T207	4