Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.10	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	5	27	84.38

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	5	27	84.38	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26483	1		T3	400		T40	576		T48	336
auto[1]	17	1		T50	5		T259	1		T261	1
auto[2]	116	1		T55	8		T57	4		T204	32
auto[3]	142	1		T1	43		T84	1		T116	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	6729	1		T1	14		T3	100		T40	144
evic_idx[1]	6687	1		T1	9		T3	100		T40	144
evic_idx[2]	6675	1		T1	8		T3	100		T40	144
evic_idx[3]	6667	1		T1	12		T3	100		T40	144

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	25990	1		T1	43		T3	400		T40	576
evic_op[2]	380	1		T84	1		T116	1		T117	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	5	27	84.38	5

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6493	1		T3	100		T40	144		T48	84
evic_idx[0]	evic_op[1]	auto[1]	1	1		T50	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	38	1		T1	14		T203	15		T318	9
evic_idx[0]	evic_op[2]	auto[0]	56	1		T54	4		T268	1		T257	10
evic_idx[0]	evic_op[2]	auto[1]	4	1		T261	1		T215	1		T319	1
evic_idx[0]	evic_op[2]	auto[2]	31	1		T204	13		T320	9		T321	9
evic_idx[0]	evic_op[2]	auto[3]	9	1		T322	1		T323	1		T324	1
evic_idx[1]	evic_op[1]	auto[0]	6469	1		T3	100		T40	144		T48	84
evic_idx[1]	evic_op[1]	auto[3]	22	1		T1	9		T203	7		T318	6
evic_idx[1]	evic_op[2]	auto[0]	54	1		T54	4		T89	1		T268	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T325	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	25	1		T204	9		T326	1		T320	4
evic_idx[1]	evic_op[2]	auto[3]	19	1		T84	1		T116	1		T117	1
evic_idx[2]	evic_op[1]	auto[0]	6466	1		T3	100		T40	144		T48	84
evic_idx[2]	evic_op[1]	auto[1]	3	1		T50	3		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	16	1		T1	8		T203	4		T318	4
evic_idx[2]	evic_op[2]	auto[0]	54	1		T52	1		T54	4		T88	1
evic_idx[2]	evic_op[2]	auto[1]	1	1		T327	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	26	1		T204	6		T263	1		T328	2
evic_idx[2]	evic_op[2]	auto[3]	12	1		T117	1		T329	1		T330	1
evic_idx[3]	evic_op[1]	auto[0]	6463	1		T3	100		T40	144		T48	84
evic_idx[3]	evic_op[1]	auto[1]	1	1		T50	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	18	1		T1	12		T203	4		T318	2
evic_idx[3]	evic_op[2]	auto[0]	56	1		T54	4		T90	1		T239	1
evic_idx[3]	evic_op[2]	auto[1]	6	1		T259	1		T331	1		T215	1
evic_idx[3]	evic_op[2]	auto[2]	18	1		T204	4		T320	6		T321	8
evic_idx[3]	evic_op[2]	auto[3]	8	1		T120	1		T332	1		T266	1