Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	39472	1		T80	4939		T81	1552		T82	5375
prog_lvl[2]	1473	1		T81	775		T393	1		T394	1
prog_lvl[3]	2	1		T81	1		T395	1		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	8167	1		T7	18		T8	1655		T21	49
rd_lvl[2]	6885	1		T7	11		T8	894		T21	8
rd_lvl[3]	3358	1		T7	13		T21	12		T162	1
rd_lvl[4]	13901	1		T7	13		T21	8		T162	1
rd_lvl[5]	13515	1		T7	10		T21	3		T162	84
rd_lvl[6]	15528	1		T7	6		T21	1		T396	667
rd_lvl[7]	11154	1		T7	272		T21	817		T397	511
rd_lvl[8]	6471	1		T7	548		T21	1190		T398	1120
rd_lvl[9]	4953	1		T7	568		T21	73		T83	591
rd_lvl[10]	3894	1		T83	528		T399	608		T212	2
rd_lvl[11]	5313	1		T7	3		T71	639		T21	3
rd_lvl[12]	6279	1		T7	42		T71	405		T21	13
rd_lvl[13]	3201	1		T83	54		T211	436		T400	532
rd_lvl[14]	2855	1		T401	44		T402	44		T403	547
rd_lvl[15]	3217	1		T271	611		T404	58		T403	346