Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	254805	1		T23	5		T63	1		T64	5
all_pins[1]	254805	1		T23	5		T63	1		T64	5
all_pins[2]	254805	1		T23	5		T63	1		T64	5
all_pins[3]	254805	1		T23	5		T63	1		T64	5
all_pins[4]	254805	1		T23	5		T63	1		T64	5
all_pins[5]	254805	1		T23	5		T63	1		T64	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1239306	1		T23	22		T63	6		T64	27
values[0x1]	289524	1		T23	8		T64	3		T230	13
transitions[0x0=>0x1]	271403	1		T23	7		T64	2		T230	12
transitions[0x1=>0x0]	271410	1		T23	7		T64	2		T230	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	210552	1		T23	3		T63	1		T64	5
all_pins[0]	values[0x1]	44253	1		T23	2		T230	5		T275	3
all_pins[0]	transitions[0x0=>0x1]	44236	1		T23	2		T230	4		T275	3
all_pins[0]	transitions[0x1=>0x0]	46290	1		T23	1		T224	2		T225	2
all_pins[1]	values[0x0]	208498	1		T23	4		T63	1		T64	5
all_pins[1]	values[0x1]	46307	1		T23	1		T230	1		T224	2
all_pins[1]	transitions[0x0=>0x1]	46289	1		T23	1		T230	1		T225	3
all_pins[1]	transitions[0x1=>0x0]	6074	1		T23	1		T275	2		T224	2
all_pins[2]	values[0x0]	248713	1		T23	4		T63	1		T64	5
all_pins[2]	values[0x1]	6092	1		T23	1		T275	2		T224	4
all_pins[2]	transitions[0x0=>0x1]	4208	1		T275	1		T224	4		T334	4
all_pins[2]	transitions[0x1=>0x0]	110899	1		T23	3		T64	2		T230	5
all_pins[3]	values[0x0]	142022	1		T23	1		T63	1		T64	3
all_pins[3]	values[0x1]	112783	1		T23	4		T64	2		T230	5
all_pins[3]	transitions[0x0=>0x1]	96625	1		T23	4		T64	1		T230	5
all_pins[3]	transitions[0x1=>0x0]	63865	1		T230	1		T231	2		T225	1
all_pins[4]	values[0x0]	174782	1		T23	5		T63	1		T64	4
all_pins[4]	values[0x1]	80023	1		T64	1		T230	1		T231	2
all_pins[4]	transitions[0x0=>0x1]	80001	1		T64	1		T230	1		T335	1
all_pins[4]	transitions[0x1=>0x0]	44	1		T230	1		T275	4		T224	1
all_pins[5]	values[0x0]	254739	1		T23	5		T63	1		T64	5
all_pins[5]	values[0x1]	66	1		T230	1		T231	2		T275	4
all_pins[5]	transitions[0x0=>0x1]	44	1		T230	1		T231	2		T275	3
all_pins[5]	transitions[0x1=>0x0]	44238	1		T23	2		T230	5		T275	2