Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16544101	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5795253	1		T12	245		T22	1126		T23	49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19110796	1		T12	381		T22	579		T23	68
values[0x0]	1613659	1		T12	106		T22	311		T23	32
values[0x1]	1614899	1		T12	102		T22	257		T23	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11072248	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	11267106	1		T12	351		T22	1135		T23	76

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	77651	1		T12	2		T22	5		T63	3
valid_sources[0x01]	67914	1		T12	1		T22	2		T65	1
valid_sources[0x02]	68807	1		T22	4		T60	47		T66	1
valid_sources[0x03]	69943	1		T22	5		T60	27		T67	2
valid_sources[0x04]	69949	1		T12	13		T22	2		T64	1
valid_sources[0x05]	75913	1		T22	3		T60	53		T144	4
valid_sources[0x06]	70539	1		T12	2		T22	1		T65	1
valid_sources[0x07]	69354	1		T22	5		T64	2		T60	43
valid_sources[0x08]	76192	1		T22	9		T60	39		T67	1
valid_sources[0x09]	78443	1		T12	13		T22	8		T60	46
valid_sources[0x0a]	70120	1		T12	7		T22	3		T60	34
valid_sources[0x0b]	69772	1		T12	12		T60	38		T62	6
valid_sources[0x0c]	170095	1		T12	1		T22	10		T60	34
valid_sources[0x0d]	95343	1		T12	2		T63	25		T60	61
valid_sources[0x0e]	97100	1		T12	3		T22	2		T65	1
valid_sources[0x0f]	69211	1		T22	10		T63	4		T65	1
valid_sources[0x10]	108704	1		T22	8		T64	5		T65	2
valid_sources[0x11]	68833	1		T12	2		T22	3		T60	54
valid_sources[0x12]	69862	1		T12	1		T60	34		T66	1
valid_sources[0x13]	93025	1		T12	1		T22	4		T63	7
valid_sources[0x14]	69874	1		T12	4		T22	4		T63	9
valid_sources[0x15]	182309	1		T12	3		T22	5		T64	8
valid_sources[0x16]	76852	1		T12	2		T22	2		T64	1
valid_sources[0x17]	92314	1		T12	7		T22	3		T60	49
valid_sources[0x18]	69686	1		T22	2		T63	10		T60	41
valid_sources[0x19]	70915	1		T12	7		T22	12		T60	41
valid_sources[0x1a]	69698	1		T12	7		T22	2		T60	51
valid_sources[0x1b]	133800	1		T12	1		T22	16		T60	37
valid_sources[0x1c]	67645	1		T22	14		T60	31		T67	1
valid_sources[0x1d]	67783	1		T12	3		T22	1		T63	3
valid_sources[0x1e]	69323	1		T12	1		T22	3		T60	14
valid_sources[0x1f]	77165	1		T12	1		T22	4		T63	102
valid_sources[0x20]	70501	1		T12	2		T22	6		T65	1
valid_sources[0x21]	69853	1		T22	6		T63	2		T65	1
valid_sources[0x22]	75112	1		T12	2		T22	5		T60	35
valid_sources[0x23]	70066	1		T22	6		T60	45		T66	1
valid_sources[0x24]	134187	1		T22	3		T60	56		T67	1
valid_sources[0x25]	230850	1		T22	2		T64	2		T60	21
valid_sources[0x26]	70594	1		T12	13		T22	4		T65	1
valid_sources[0x27]	70469	1		T12	4		T22	2		T60	70
valid_sources[0x28]	70154	1		T12	1		T22	8		T63	12
valid_sources[0x29]	91317	1		T22	6		T60	29		T67	1
valid_sources[0x2a]	69522	1		T22	8		T60	38		T66	1
valid_sources[0x2b]	103863	1		T12	7		T22	5		T60	49
valid_sources[0x2c]	68695	1		T22	5		T60	38		T66	1
valid_sources[0x2d]	70973	1		T22	3		T60	40		T67	2
valid_sources[0x2e]	138921	1		T12	5		T22	6		T63	9
valid_sources[0x2f]	102841	1		T12	2		T60	50		T61	1
valid_sources[0x30]	125725	1		T12	11		T22	1		T64	4
valid_sources[0x31]	70105	1		T12	1		T22	1		T60	68
valid_sources[0x32]	70517	1		T22	3		T60	27		T67	1
valid_sources[0x33]	133491	1		T22	1		T60	46		T61	5
valid_sources[0x34]	69419	1		T12	9		T22	2		T60	38
valid_sources[0x35]	70443	1		T22	6		T63	5		T60	47
valid_sources[0x36]	91179	1		T22	4		T64	1		T60	29
valid_sources[0x37]	159725	1		T12	4		T22	7		T60	47
valid_sources[0x38]	70642	1		T12	1		T22	3		T65	1
valid_sources[0x39]	67734	1		T12	6		T22	2		T64	1
valid_sources[0x3a]	68681	1		T22	1		T63	5		T60	56
valid_sources[0x3b]	69697	1		T22	7		T64	1		T65	1
valid_sources[0x3c]	68317	1		T22	3		T60	49		T61	4
valid_sources[0x3d]	71199	1		T12	7		T22	7		T60	48
valid_sources[0x3e]	135706	1		T22	3		T60	52		T144	4
valid_sources[0x3f]	68699	1		T12	2		T22	5		T64	11
valid_sources[0x40]	68900	1		T12	10		T22	11		T60	42
valid_sources[0x41]	69308	1		T12	6		T22	4		T60	51
valid_sources[0x42]	102688	1		T22	1		T64	1		T60	49
valid_sources[0x43]	70750	1		T22	7		T23	124		T60	41
valid_sources[0x44]	68617	1		T12	9		T22	2		T65	1
valid_sources[0x45]	71219	1		T12	14		T22	6		T63	1
valid_sources[0x46]	68988	1		T22	10		T60	70		T67	1
valid_sources[0x47]	92654	1		T22	3		T63	1		T65	1
valid_sources[0x48]	142929	1		T12	3		T22	7		T63	1
valid_sources[0x49]	69232	1		T22	9		T63	5		T60	32
valid_sources[0x4a]	69010	1		T12	1		T65	1		T60	32
valid_sources[0x4b]	184434	1		T22	4		T60	32		T67	1
valid_sources[0x4c]	69523	1		T12	4		T22	9		T60	53
valid_sources[0x4d]	68685	1		T12	17		T22	5		T60	67
valid_sources[0x4e]	69831	1		T22	10		T65	1		T60	39
valid_sources[0x4f]	67697	1		T12	3		T22	6		T65	1
valid_sources[0x50]	67326	1		T12	2		T22	3		T60	26
valid_sources[0x51]	84504	1		T12	5		T22	10		T60	62
valid_sources[0x52]	67867	1		T22	6		T63	4		T60	52
valid_sources[0x53]	70676	1		T22	7		T60	44		T67	1
valid_sources[0x54]	70703	1		T22	1		T63	16		T60	41
valid_sources[0x55]	91275	1		T12	1		T22	5		T60	28
valid_sources[0x56]	69034	1		T22	7		T63	7		T60	32
valid_sources[0x57]	68851	1		T12	7		T22	4		T60	37
valid_sources[0x58]	67854	1		T12	2		T22	9		T60	60
valid_sources[0x59]	74250	1		T12	5		T22	3		T60	15
valid_sources[0x5a]	69456	1		T12	5		T22	5		T60	50
valid_sources[0x5b]	75107	1		T22	2		T60	44		T62	4
valid_sources[0x5c]	87728	1		T22	7		T60	43		T66	1
valid_sources[0x5d]	71111	1		T12	2		T22	2		T63	4
valid_sources[0x5e]	123628	1		T64	3		T60	48		T67	1
valid_sources[0x5f]	69786	1		T12	1		T22	8		T60	41
valid_sources[0x60]	68680	1		T12	2		T22	9		T65	1
valid_sources[0x61]	85366	1		T22	6		T60	36		T61	5
valid_sources[0x62]	69844	1		T22	4		T63	4		T65	1
valid_sources[0x63]	67487	1		T12	3		T22	4		T60	41
valid_sources[0x64]	84084	1		T22	10		T60	56		T61	3
valid_sources[0x65]	138141	1		T12	7		T63	7		T60	26
valid_sources[0x66]	179309	1		T22	5		T64	1		T60	49
valid_sources[0x67]	74650	1		T12	3		T60	24		T67	1
valid_sources[0x68]	68865	1		T12	1		T22	5		T65	1
valid_sources[0x69]	68623	1		T22	14		T60	29		T66	1
valid_sources[0x6a]	174788	1		T12	2		T22	2		T63	3
valid_sources[0x6b]	68938	1		T12	1		T22	6		T65	1
valid_sources[0x6c]	70139	1		T12	2		T22	1		T60	41
valid_sources[0x6d]	69317	1		T22	3		T65	1		T60	54
valid_sources[0x6e]	70435	1		T22	2		T64	3		T60	58
valid_sources[0x6f]	70601	1		T63	2		T65	1		T60	21
valid_sources[0x70]	145197	1		T22	8		T60	38		T62	4
valid_sources[0x71]	126261	1		T22	1		T60	28		T67	1
valid_sources[0x72]	70875	1		T22	3		T60	33		T67	1
valid_sources[0x73]	96259	1		T22	13		T64	1		T60	37
valid_sources[0x74]	95906	1		T12	13		T22	5		T60	30
valid_sources[0x75]	68741	1		T22	6		T63	8		T60	38
valid_sources[0x76]	69449	1		T22	7		T60	53		T67	1
valid_sources[0x77]	69055	1		T12	3		T22	4		T65	1
valid_sources[0x78]	91861	1		T22	2		T60	53		T67	1
valid_sources[0x79]	70316	1		T12	8		T60	20		T67	1
valid_sources[0x7a]	93268	1		T22	5		T63	11		T64	2
valid_sources[0x7b]	69066	1		T12	3		T22	2		T65	1
valid_sources[0x7c]	81338	1		T12	2		T22	4		T63	7
valid_sources[0x7d]	76114	1		T22	1		T65	1		T60	42
valid_sources[0x7e]	232508	1		T22	3		T63	2		T60	32
valid_sources[0x7f]	73693	1		T22	5		T60	33		T66	2
valid_sources[0x80]	77260	1		T12	22		T22	3		T60	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3041716

1

T12

115

T22

558

T23

6

values[0x0]

all_enables

biggest_size

1444754

1

T12

73

T22

311

T23

28

values[0x1]

all_enables

biggest_size

1308783

1

T12

57

T22

257

T23

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1800	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3517223	1		T63	538		T60	1		T67	370

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3512329	1		T63	133		T60	6		T67	90
values[0x0]	2655	1		T63	200		T60	1		T67	140
values[0x1]	4039	1		T63	272		T60	9		T67	203

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	659	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3518364	1		T63	579		T60	10		T67	411

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13878	1		T67	1		T62	1		T149	1
valid_sources[0x01]	13621	1		T67	6		T62	1		T149	3
valid_sources[0x02]	13813	1		T67	1		T62	5		T149	5
valid_sources[0x03]	13180	1		T67	3		T62	8		T149	2
valid_sources[0x04]	13377	1		T67	2		T62	5		T145	1
valid_sources[0x05]	13621	1		T62	4		T252	1		T4	126
valid_sources[0x06]	13885	1		T67	1		T62	2		T4	144
valid_sources[0x07]	13466	1		T67	1		T61	4		T62	1
valid_sources[0x08]	13862	1		T67	1		T61	1		T62	5
valid_sources[0x09]	13731	1		T62	2		T234	1		T149	8
valid_sources[0x0a]	13586	1		T67	1		T61	1		T62	3
valid_sources[0x0b]	13713	1		T67	6		T61	4		T62	3
valid_sources[0x0c]	13834	1		T63	152		T67	2		T149	1
valid_sources[0x0d]	13738	1		T61	1		T62	1		T149	3
valid_sources[0x0e]	13931	1		T67	2		T149	1		T150	1
valid_sources[0x0f]	13983	1		T67	1		T62	2		T149	3
valid_sources[0x10]	13951	1		T67	3		T62	2		T245	1
valid_sources[0x11]	13652	1		T62	1		T146	1		T4	172
valid_sources[0x12]	13566	1		T62	5		T149	2		T150	3
valid_sources[0x13]	13785	1		T67	1		T61	2		T62	2
valid_sources[0x14]	13539	1		T67	2		T62	3		T149	2
valid_sources[0x15]	13345	1		T67	1		T149	1		T4	195
valid_sources[0x16]	13777	1		T67	8		T62	5		T149	2
valid_sources[0x17]	13917	1		T61	1		T146	1		T149	2
valid_sources[0x18]	14229	1		T67	2		T62	2		T149	2
valid_sources[0x19]	13587	1		T67	3		T61	1		T62	1
valid_sources[0x1a]	13805	1		T67	2		T62	3		T145	1
valid_sources[0x1b]	14019	1		T67	2		T62	2		T145	1
valid_sources[0x1c]	13853	1		T67	2		T62	2		T234	1
valid_sources[0x1d]	13741	1		T67	5		T61	2		T62	6
valid_sources[0x1e]	13729	1		T67	2		T62	1		T149	3
valid_sources[0x1f]	13608	1		T67	5		T61	1		T62	1
valid_sources[0x20]	13466	1		T67	1		T62	5		T149	8
valid_sources[0x21]	13407	1		T61	1		T62	2		T149	1
valid_sources[0x22]	13743	1		T67	3		T62	1		T149	2
valid_sources[0x23]	13945	1		T67	1		T61	2		T62	1
valid_sources[0x24]	13435	1		T67	2		T61	3		T62	2
valid_sources[0x25]	13942	1		T61	1		T62	1		T149	1
valid_sources[0x26]	13802	1		T67	3		T62	3		T149	3
valid_sources[0x27]	13610	1		T62	2		T149	1		T4	128
valid_sources[0x28]	13801	1		T67	1		T61	2		T62	2
valid_sources[0x29]	13773	1		T67	1		T62	2		T149	4
valid_sources[0x2a]	13680	1		T67	1		T62	2		T147	2
valid_sources[0x2b]	13394	1		T67	2		T147	1		T149	6
valid_sources[0x2c]	13798	1		T67	2		T61	1		T149	2
valid_sources[0x2d]	13820	1		T67	3		T62	2		T146	1
valid_sources[0x2e]	13580	1		T61	2		T62	4		T4	129
valid_sources[0x2f]	14257	1		T67	2		T62	2		T149	2
valid_sources[0x30]	14160	1		T63	123		T62	6		T245	1
valid_sources[0x31]	14134	1		T67	1		T62	2		T145	1
valid_sources[0x32]	13643	1		T67	1		T62	1		T149	1
valid_sources[0x33]	14051	1		T61	4		T62	6		T146	1
valid_sources[0x34]	13696	1		T67	1		T61	2		T62	7
valid_sources[0x35]	13347	1		T67	1		T62	2		T150	1
valid_sources[0x36]	13879	1		T146	1		T149	2		T150	2
valid_sources[0x37]	13473	1		T67	2		T61	2		T62	2
valid_sources[0x38]	13922	1		T67	2		T61	2		T62	3
valid_sources[0x39]	13593	1		T67	4		T61	2		T62	2
valid_sources[0x3a]	13465	1		T67	2		T62	3		T149	1
valid_sources[0x3b]	13971	1		T67	2		T62	3		T149	1
valid_sources[0x3c]	13518	1		T67	3		T61	2		T62	4
valid_sources[0x3d]	13849	1		T67	2		T62	2		T149	2
valid_sources[0x3e]	13851	1		T67	3		T61	3		T62	6
valid_sources[0x3f]	14274	1		T62	3		T149	4		T4	150
valid_sources[0x40]	13696	1		T61	1		T62	2		T149	1
valid_sources[0x41]	13646	1		T149	2		T4	208		T7	52
valid_sources[0x42]	14002	1		T67	1		T62	3		T4	218
valid_sources[0x43]	13606	1		T67	1		T62	1		T145	1
valid_sources[0x44]	13816	1		T67	3		T61	6		T62	2
valid_sources[0x45]	13267	1		T67	3		T62	6		T145	2
valid_sources[0x46]	14010	1		T67	1		T62	1		T149	4
valid_sources[0x47]	13520	1		T67	1		T62	1		T149	1
valid_sources[0x48]	14010	1		T67	1		T61	6		T62	3
valid_sources[0x49]	13822	1		T67	1		T61	1		T62	2
valid_sources[0x4a]	14210	1		T62	1		T4	106		T19	1
valid_sources[0x4b]	13493	1		T67	2		T61	1		T62	2
valid_sources[0x4c]	13737	1		T67	1		T62	3		T146	1
valid_sources[0x4d]	13868	1		T67	3		T61	5		T245	1
valid_sources[0x4e]	13806	1		T67	1		T61	2		T62	4
valid_sources[0x4f]	13932	1		T62	4		T149	4		T4	194
valid_sources[0x50]	13870	1		T67	1		T62	1		T149	1
valid_sources[0x51]	13547	1		T144	170		T62	4		T146	1
valid_sources[0x52]	13673	1		T62	2		T4	137		T7	78
valid_sources[0x53]	13881	1		T67	1		T61	1		T62	2
valid_sources[0x54]	13642	1		T149	4		T4	171		T7	35
valid_sources[0x55]	13679	1		T67	1		T62	1		T149	1
valid_sources[0x56]	13761	1		T67	4		T149	1		T4	235
valid_sources[0x57]	13754	1		T62	1		T149	1		T405	2
valid_sources[0x58]	13766	1		T67	3		T62	1		T234	1
valid_sources[0x59]	13632	1		T67	4		T61	4		T62	4
valid_sources[0x5a]	14036	1		T147	16		T149	3		T4	157
valid_sources[0x5b]	13658	1		T67	1		T61	1		T62	2
valid_sources[0x5c]	13391	1		T67	1		T62	1		T145	1
valid_sources[0x5d]	13945	1		T67	4		T61	5		T62	2
valid_sources[0x5e]	13712	1		T67	2		T61	1		T62	1
valid_sources[0x5f]	13632	1		T67	1		T61	1		T62	4
valid_sources[0x60]	13523	1		T67	3		T61	4		T62	2
valid_sources[0x61]	13683	1		T67	3		T62	1		T145	1
valid_sources[0x62]	13888	1		T67	1		T62	1		T252	1
valid_sources[0x63]	13609	1		T67	2		T61	1		T62	2
valid_sources[0x64]	13298	1		T67	1		T62	1		T147	5
valid_sources[0x65]	13755	1		T67	6		T62	2		T149	1
valid_sources[0x66]	14109	1		T67	1		T62	1		T146	1
valid_sources[0x67]	13303	1		T67	1		T62	2		T145	1
valid_sources[0x68]	13611	1		T67	3		T62	3		T149	1
valid_sources[0x69]	13561	1		T67	2		T62	2		T234	1
valid_sources[0x6a]	13891	1		T67	1		T62	2		T4	110
valid_sources[0x6b]	13769	1		T67	3		T62	3		T149	2
valid_sources[0x6c]	13871	1		T67	3		T62	1		T149	1
valid_sources[0x6d]	13705	1		T67	2		T62	4		T149	6
valid_sources[0x6e]	13926	1		T61	1		T62	4		T149	3
valid_sources[0x6f]	14106	1		T67	2		T61	1		T62	3
valid_sources[0x70]	13623	1		T67	2		T62	2		T149	2
valid_sources[0x71]	13381	1		T67	2		T61	5		T62	5
valid_sources[0x72]	13700	1		T67	1		T245	2		T149	4
valid_sources[0x73]	13778	1		T67	2		T61	1		T62	5
valid_sources[0x74]	13537	1		T67	3		T62	2		T145	1
valid_sources[0x75]	13751	1		T67	2		T62	1		T149	3
valid_sources[0x76]	13920	1		T67	3		T62	5		T149	3
valid_sources[0x77]	13725	1		T61	4		T62	7		T146	1
valid_sources[0x78]	13465	1		T67	1		T61	5		T62	4
valid_sources[0x79]	13810	1		T67	4		T61	4		T62	4
valid_sources[0x7a]	13867	1		T62	2		T145	1		T149	3
valid_sources[0x7b]	13423	1		T62	3		T149	1		T4	177
valid_sources[0x7c]	13694	1		T67	1		T149	3		T4	147
valid_sources[0x7d]	14321	1		T67	4		T61	2		T62	4
valid_sources[0x7e]	13016	1		T67	1		T62	2		T149	2
valid_sources[0x7f]	13681	1		T67	1		T149	1		T4	158
valid_sources[0x80]	13883	1		T67	2		T62	6		T145	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3512228

1

T63

133

T67

90

T61

47

values[0x0]

all_enables

biggest_size

2500

1

T63

191

T60

1

T67

134

values[0x1]

all_enables

biggest_size

2495

1

T63

214

T67

146

T61

66

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32783	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	32126	1		T12	43		T63	398		T60	391

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	41174	1		T12	42		T63	122		T60	828
values[0x0]	11585	1		T12	21		T63	145		T60	234
values[0x1]	12150	1		T12	21		T63	184		T60	193

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23810	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	41099	1		T12	52		T63	431		T60	682

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	146	1		T12	1		T63	1		T245	10
valid_sources[0x01]	276	1		T245	2		T254	6		T406	7
valid_sources[0x02]	147	1		T12	1		T233	30		T245	3
valid_sources[0x03]	134	1		T63	1		T245	7		T254	2
valid_sources[0x04]	224	1		T63	2		T144	3		T145	1
valid_sources[0x05]	1014	1		T61	1		T145	1		T245	6
valid_sources[0x06]	118	1		T63	1		T61	2		T245	4
valid_sources[0x07]	247	1		T63	3		T144	18		T233	64
valid_sources[0x08]	139	1		T12	1		T63	3		T145	1
valid_sources[0x09]	105	1		T245	1		T277	9		T254	12
valid_sources[0x0a]	158	1		T234	2		T245	14		T277	18
valid_sources[0x0b]	823	1		T63	1		T61	1		T234	19
valid_sources[0x0c]	904	1		T63	3		T145	3		T245	5
valid_sources[0x0d]	184	1		T63	4		T144	8		T245	7
valid_sources[0x0e]	149	1		T63	1		T145	1		T233	27
valid_sources[0x0f]	197	1		T144	7		T245	3		T254	8
valid_sources[0x10]	1080	1		T63	1		T145	1		T245	7
valid_sources[0x11]	115	1		T63	2		T245	8		T254	7
valid_sources[0x12]	145	1		T63	5		T245	7		T254	2
valid_sources[0x13]	230	1		T145	1		T233	60		T245	2
valid_sources[0x14]	1152	1		T63	2		T67	1		T245	11
valid_sources[0x15]	156	1		T61	2		T62	12		T145	1
valid_sources[0x16]	122	1		T245	2		T254	3		T278	1
valid_sources[0x17]	222	1		T63	4		T67	2		T144	8
valid_sources[0x18]	188	1		T234	2		T245	9		T254	4
valid_sources[0x19]	184	1		T63	5		T145	1		T245	10
valid_sources[0x1a]	197	1		T63	2		T245	6		T146	3
valid_sources[0x1b]	149	1		T245	6		T254	10		T278	25
valid_sources[0x1c]	176	1		T12	1		T63	5		T144	3
valid_sources[0x1d]	292	1		T12	2		T67	1		T245	2
valid_sources[0x1e]	256	1		T12	2		T63	5		T245	8
valid_sources[0x1f]	186	1		T63	3		T245	10		T277	9
valid_sources[0x20]	407	1		T144	131		T245	7		T277	18
valid_sources[0x21]	875	1		T63	2		T245	5		T254	3
valid_sources[0x22]	1443	1		T12	1		T63	1		T67	2
valid_sources[0x23]	1161	1		T63	3		T61	1		T62	4
valid_sources[0x24]	183	1		T61	2		T62	10		T145	1
valid_sources[0x25]	160	1		T63	4		T144	11		T245	2
valid_sources[0x26]	268	1		T63	2		T233	71		T234	11
valid_sources[0x27]	166	1		T12	1		T63	4		T245	8
valid_sources[0x28]	124	1		T12	1		T234	2		T245	2
valid_sources[0x29]	116	1		T63	2		T245	2		T254	8
valid_sources[0x2a]	162	1		T63	4		T145	1		T245	1
valid_sources[0x2b]	1123	1		T61	1		T145	2		T245	2
valid_sources[0x2c]	100	1		T12	1		T63	3		T61	5
valid_sources[0x2d]	151	1		T234	4		T245	4		T254	7
valid_sources[0x2e]	123	1		T61	2		T245	5		T297	17
valid_sources[0x2f]	169	1		T63	1		T67	1		T234	14
valid_sources[0x30]	191	1		T63	3		T144	2		T245	4
valid_sources[0x31]	215	1		T63	4		T145	1		T245	3
valid_sources[0x32]	174	1		T63	2		T234	4		T245	3
valid_sources[0x33]	192	1		T63	1		T60	31		T145	3
valid_sources[0x34]	140	1		T234	2		T245	4		T254	3
valid_sources[0x35]	142	1		T63	2		T145	2		T245	4
valid_sources[0x36]	271	1		T63	1		T67	1		T62	5
valid_sources[0x37]	200	1		T234	1		T245	9		T277	46
valid_sources[0x38]	145	1		T63	2		T60	29		T245	10
valid_sources[0x39]	171	1		T234	16		T245	7		T277	18
valid_sources[0x3a]	345	1		T63	3		T60	188		T245	2
valid_sources[0x3b]	236	1		T63	2		T234	2		T245	7
valid_sources[0x3c]	168	1		T12	1		T63	1		T245	7
valid_sources[0x3d]	145	1		T63	1		T60	33		T245	2
valid_sources[0x3e]	268	1		T63	1		T60	66		T245	4
valid_sources[0x3f]	176	1		T63	1		T67	3		T234	5
valid_sources[0x40]	300	1		T63	2		T144	166		T245	8
valid_sources[0x41]	214	1		T63	4		T144	10		T234	19
valid_sources[0x42]	355	1		T12	1		T63	4		T60	158
valid_sources[0x43]	188	1		T63	2		T67	1		T233	87
valid_sources[0x44]	131	1		T63	2		T234	9		T245	5
valid_sources[0x45]	218	1		T12	1		T63	2		T234	37
valid_sources[0x46]	129	1		T145	2		T245	4		T254	3
valid_sources[0x47]	115	1		T145	1		T245	6		T254	5
valid_sources[0x48]	110	1		T12	3		T63	2		T61	1
valid_sources[0x49]	212	1		T63	1		T234	1		T245	4
valid_sources[0x4a]	224	1		T63	2		T60	69		T245	4
valid_sources[0x4b]	115	1		T12	1		T63	2		T145	1
valid_sources[0x4c]	195	1		T145	1		T245	4		T277	45
valid_sources[0x4d]	108	1		T12	1		T245	2		T254	5
valid_sources[0x4e]	124	1		T63	1		T62	10		T245	9
valid_sources[0x4f]	217	1		T63	4		T60	38		T233	60
valid_sources[0x50]	117	1		T63	1		T61	3		T234	9
valid_sources[0x51]	161	1		T63	2		T61	5		T145	1
valid_sources[0x52]	137	1		T12	1		T63	2		T145	1
valid_sources[0x53]	242	1		T63	2		T61	1		T234	6
valid_sources[0x54]	107	1		T12	1		T61	2		T245	5
valid_sources[0x55]	136	1		T63	1		T61	2		T245	5
valid_sources[0x56]	171	1		T63	3		T145	1		T234	12
valid_sources[0x57]	256	1		T63	1		T245	2		T254	4
valid_sources[0x58]	276	1		T63	2		T61	4		T233	71
valid_sources[0x59]	154	1		T12	2		T63	1		T61	1
valid_sources[0x5a]	254	1		T12	2		T63	1		T61	1
valid_sources[0x5b]	1059	1		T63	2		T245	6		T277	18
valid_sources[0x5c]	252	1		T12	1		T63	1		T61	2
valid_sources[0x5d]	205	1		T63	2		T67	1		T245	5
valid_sources[0x5e]	95	1		T245	3		T254	5		T406	4
valid_sources[0x5f]	142	1		T12	1		T63	2		T245	4
valid_sources[0x60]	197	1		T67	1		T145	1		T234	7
valid_sources[0x61]	126	1		T12	1		T63	1		T145	1
valid_sources[0x62]	191	1		T63	2		T245	5		T254	6
valid_sources[0x63]	182	1		T61	2		T145	1		T245	3
valid_sources[0x64]	245	1		T12	2		T63	1		T61	1
valid_sources[0x65]	169	1		T63	1		T234	10		T245	4
valid_sources[0x66]	112	1		T63	1		T245	5		T254	6
valid_sources[0x67]	125	1		T63	4		T67	1		T144	8
valid_sources[0x68]	110	1		T61	7		T245	8		T254	9
valid_sources[0x69]	105	1		T245	3		T277	18		T254	10
valid_sources[0x6a]	295	1		T245	8		T277	18		T254	6
valid_sources[0x6b]	172	1		T63	1		T245	5		T146	2
valid_sources[0x6c]	136	1		T67	1		T245	3		T277	18
valid_sources[0x6d]	206	1		T12	2		T63	3		T61	3
valid_sources[0x6e]	260	1		T63	4		T61	4		T245	5
valid_sources[0x6f]	107	1		T63	2		T245	3		T146	1
valid_sources[0x70]	187	1		T12	1		T63	2		T144	9
valid_sources[0x71]	220	1		T12	2		T63	3		T61	4
valid_sources[0x72]	226	1		T63	1		T67	1		T234	9
valid_sources[0x73]	87	1		T63	2		T245	1		T254	1
valid_sources[0x74]	777	1		T12	1		T63	3		T245	6
valid_sources[0x75]	1821	1		T12	2		T63	2		T60	27
valid_sources[0x76]	108	1		T12	1		T63	3		T62	5
valid_sources[0x77]	197	1		T63	1		T61	8		T234	2
valid_sources[0x78]	157	1		T12	1		T63	2		T145	1
valid_sources[0x79]	133	1		T63	2		T144	31		T245	4
valid_sources[0x7a]	181	1		T63	3		T67	1		T61	1
valid_sources[0x7b]	143	1		T63	2		T234	7		T245	6
valid_sources[0x7c]	156	1		T63	2		T234	7		T245	3
valid_sources[0x7d]	162	1		T63	2		T60	31		T145	1
valid_sources[0x7e]	111	1		T63	1		T61	1		T234	1
valid_sources[0x7f]	161	1		T63	5		T234	8		T245	12
valid_sources[0x80]	136	1		T63	1		T67	1		T245	3