Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	293	1		T23	4		T64	4		T230	7
all_values[1]	293	1		T23	4		T64	4		T230	7
all_values[2]	293	1		T23	4		T64	4		T230	7
all_values[3]	293	1		T23	4		T64	4		T230	7
all_values[4]	293	1		T23	4		T64	4		T230	7
all_values[5]	293	1		T23	4		T64	4		T230	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	926	1		T23	11		T64	17		T230	25
auto[1]	832	1		T23	13		T64	7		T230	17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	688	1		T23	7		T64	10		T230	15
auto[1]	1070	1		T23	17		T64	14		T230	27

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1035	1		T23	15		T64	14		T230	20
auto[1]	723	1		T23	9		T64	10		T230	22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	63	1		T64	1		T231	2		T224	2
all_values[0]	auto[0]	auto[0]	auto[1]	26	1		T64	1		T231	1		T275	2
all_values[0]	auto[0]	auto[1]	auto[0]	54	1		T224	1		T225	2		T335	1
all_values[0]	auto[0]	auto[1]	auto[1]	34	1		T23	2		T230	2		T275	2
all_values[0]	auto[1]	auto[0]	auto[1]	62	1		T23	2		T64	2		T230	2
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T230	3		T275	1		T334	1
all_values[1]	auto[0]	auto[0]	auto[0]	60	1		T64	2		T230	6		T231	1
all_values[1]	auto[0]	auto[0]	auto[1]	34	1		T23	2		T224	1		T225	1
all_values[1]	auto[0]	auto[1]	auto[0]	53	1		T23	1		T64	2		T231	3
all_values[1]	auto[0]	auto[1]	auto[1]	27	1		T225	1		T335	1		T295	1
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T275	2		T224	1		T334	2
all_values[1]	auto[1]	auto[1]	auto[1]	55	1		T23	1		T230	1		T224	4
all_values[2]	auto[0]	auto[0]	auto[0]	69	1		T230	3		T231	2		T224	1
all_values[2]	auto[0]	auto[0]	auto[1]	24	1		T64	1		T230	1		T275	2
all_values[2]	auto[0]	auto[1]	auto[0]	46	1		T23	3		T231	2		T224	1
all_values[2]	auto[0]	auto[1]	auto[1]	34	1		T224	1		T334	2		T225	1
all_values[2]	auto[1]	auto[0]	auto[1]	54	1		T64	2		T230	2		T275	3
all_values[2]	auto[1]	auto[1]	auto[1]	66	1		T23	1		T64	1		T230	1
all_values[3]	auto[0]	auto[0]	auto[0]	65	1		T230	2		T231	1		T275	1
all_values[3]	auto[0]	auto[0]	auto[1]	25	1		T64	1		T224	1		T335	1
all_values[3]	auto[0]	auto[1]	auto[0]	41	1		T231	2		T334	3		T225	2
all_values[3]	auto[0]	auto[1]	auto[1]	29	1		T23	2		T230	1		T275	3
all_values[3]	auto[1]	auto[0]	auto[1]	71	1		T64	2		T275	1		T224	2
all_values[3]	auto[1]	auto[1]	auto[1]	62	1		T23	2		T64	1		T230	4
all_values[4]	auto[0]	auto[0]	auto[0]	80	1		T23	1		T64	2		T231	1
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T23	1		T334	1		T225	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1		T230	2		T231	1		T224	2
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T64	1		T231	1		T226	1
all_values[4]	auto[1]	auto[0]	auto[1]	47	1		T23	2		T64	1		T230	3
all_values[4]	auto[1]	auto[1]	auto[1]	67	1		T230	2		T231	1		T334	1
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T23	1		T64	1		T230	2
all_values[5]	auto[0]	auto[0]	auto[1]	32	1		T23	1		T230	1		T224	3
all_values[5]	auto[0]	auto[1]	auto[0]	55	1		T23	1		T64	2		T334	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T231	1		T275	3		T334	2
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T23	1		T64	1		T230	3
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T230	1		T231	1		T275	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal