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 LINE       11942
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b0111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b0111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b0111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | 
     58  (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | 
     59  (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | 
     60  (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | 
     61  (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | 
     62  (addr_hit[61] & ((|(4'b1111 & (~reg_be))))) | 
     63  (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) | 
     64  (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | 
     65  (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | 
     66  (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | 
     67  (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | 
     68  (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | 
     69  (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | 
     70  (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | 
     71  (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | 
     72  (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | 
     73  (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | 
     74  (addr_hit[73] & ((|(4'b1111 & (~reg_be))))) | 
     75  (addr_hit[74] & ((|(4'b1111 & (~reg_be))))) | 
     76  (addr_hit[75] & ((|(4'b1111 & (~reg_be))))) | 
     77  (addr_hit[76] & ((|(4'b1111 & (~reg_be))))) | 
     78  (addr_hit[77] & ((|(4'b1111 & (~reg_be))))) | 
     79  (addr_hit[78] & ((|(4'b1111 & (~reg_be))))) | 
     80  (addr_hit[79] & ((|(4'b1111 & (~reg_be))))) | 
     81  (addr_hit[80] & ((|(4'b1111 & (~reg_be))))) | 
     82  (addr_hit[81] & ((|(4'b1111 & (~reg_be))))) | 
     83  (addr_hit[82] & ((|(4'b1111 & (~reg_be))))) | 
     84  (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | 
     85  (addr_hit[84] & ((|(4'b1111 & (~reg_be))))) | 
     86  (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | 
     87  (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | 
     88  (addr_hit[87] & ((|(4'b1111 & (~reg_be))))) | 
     89  (addr_hit[88] & ((|(4'b1111 & (~reg_be))))) | 
     90  (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | 
     91  (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | 
     92  (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | 
     93  (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | 
     94  (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | 
     95  (addr_hit[94] & ((|(4'b0011 & (~reg_be))))) | 
     96  (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | 
     97  (addr_hit[96] & ((|(4'b0011 & (~reg_be))))) | 
     98  (addr_hit[97] & ((|(4'b0011 & (~reg_be))))) | 
     99  (addr_hit[98] & ((|(4'b0111 & (~reg_be))))) | 
    100  (addr_hit[99] & ((|(4'b0011 & (~reg_be))))) | 
    101  (addr_hit[100] & ((|(4'b0111 & (~reg_be))))) | 
    102  (addr_hit[101] & ((|(4'b0111 & (~reg_be))))) | 
    103  (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | 
    104  (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | 
    105  (addr_hit[104] & ((|(4'b1111 & (~reg_be))))) | 
    106  (addr_hit[105] & ((|(4'b0011 & (~reg_be))))) | 
    107  (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | 
    108  (addr_hit[107] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T12,T22,T23
108 (addr_hit[107] & ((\|(4...	Covered	T12,T63,T64
107 (addr_hit[106] & ((\|(4...	Covered	T12,T63,T60
106 (addr_hit[105] & ((\|(4...	Covered	T12,T63,T64
105 (addr_hit[104] & ((\|(4...	Covered	T12,T63,T60
104 (addr_hit[103] & ((\|(4...	Covered	T12,T63,T60
103 (addr_hit[102] & ((\|(4...	Covered	T12,T63,T64
102 (addr_hit[101] & ((\|(4...	Covered	T12,T63,T64
101 (addr_hit[100] & ((\|(4...	Covered	T12,T63,T60
100 (addr_hit[99] & ((\|(4'...	Covered	T12,T63,T60
99 (addr_hit[98] & ((\|(4'...	Covered	T12,T63,T60
98 (addr_hit[97] & ((\|(4'...	Covered	T12,T63,T64
97 (addr_hit[96] & ((\|(4'...	Covered	T63,T60,T67
96 (addr_hit[95] & ((\|(4'...	Covered	T12,T63,T64
95 (addr_hit[94] & ((\|(4'...	Covered	T12,T63,T64
94 (addr_hit[93] & ((\|(4'...	Covered	T12,T63,T60
93 (addr_hit[92] & ((\|(4'...	Covered	T12,T63,T64
92 (addr_hit[91] & ((\|(4'...	Covered	T12,T63,T60
91 (addr_hit[90] & ((\|(4'...	Covered	T12,T63,T60
90 (addr_hit[89] & ((\|(4'...	Covered	T12,T63,T64
89 (addr_hit[88] & ((\|(4'...	Covered	T12,T63,T60
88 (addr_hit[87] & ((\|(4'...	Covered	T12,T63,T60
87 (addr_hit[86] & ((\|(4'...	Covered	T12,T63,T60
86 (addr_hit[85] & ((\|(4'...	Covered	T63,T64,T60
85 (addr_hit[84] & ((\|(4'...	Covered	T12,T63,T60
84 (addr_hit[83] & ((\|(4'...	Covered	T12,T63,T60
83 (addr_hit[82] & ((\|(4'...	Covered	T12,T63,T64
82 (addr_hit[81] & ((\|(4'...	Covered	T12,T63,T60
81 (addr_hit[80] & ((\|(4'...	Covered	T12,T63,T64
80 (addr_hit[79] & ((\|(4'...	Covered	T12,T63,T60
79 (addr_hit[78] & ((\|(4'...	Covered	T12,T63,T64
78 (addr_hit[77] & ((\|(4'...	Covered	T12,T63,T64
77 (addr_hit[76] & ((\|(4'...	Covered	T12,T63,T64
76 (addr_hit[75] & ((\|(4'...	Covered	T12,T63,T64
75 (addr_hit[74] & ((\|(4'...	Covered	T12,T63,T64
74 (addr_hit[73] & ((\|(4'...	Covered	T12,T63,T64
73 (addr_hit[72] & ((\|(4'...	Covered	T12,T63,T60
72 (addr_hit[71] & ((\|(4'...	Covered	T12,T63,T60
71 (addr_hit[70] & ((\|(4'...	Covered	T12,T63,T60
70 (addr_hit[69] & ((\|(4'...	Covered	T12,T63,T64
69 (addr_hit[68] & ((\|(4'...	Covered	T12,T63,T60
68 (addr_hit[67] & ((\|(4'...	Covered	T12,T63,T60
67 (addr_hit[66] & ((\|(4'...	Covered	T12,T63,T60
66 (addr_hit[65] & ((\|(4'...	Covered	T12,T63,T64
65 (addr_hit[64] & ((\|(4'...	Covered	T12,T63,T64
64 (addr_hit[63] & ((\|(4'...	Covered	T12,T63,T60
63 (addr_hit[62] & ((\|(4'...	Covered	T12,T63,T64
62 (addr_hit[61] & ((\|(4'...	Covered	T12,T63,T60
61 (addr_hit[60] & ((\|(4'...	Covered	T12,T63,T60
60 (addr_hit[59] & ((\|(4'...	Covered	T12,T63,T60
59 (addr_hit[58] & ((\|(4'...	Covered	T12,T63,T64
58 (addr_hit[57] & ((\|(4'...	Covered	T12,T63,T60
57 (addr_hit[56] & ((\|(4'...	Covered	T12,T63,T60
56 (addr_hit[55] & ((\|(4'...	Covered	T12,T63,T64
55 (addr_hit[54] & ((\|(4'...	Covered	T12,T63,T64
54 (addr_hit[53] & ((\|(4'...	Covered	T12,T63,T64
53 (addr_hit[52] & ((\|(4'...	Covered	T12,T63,T64
52 (addr_hit[51] & ((\|(4'...	Covered	T12,T63,T64
51 (addr_hit[50] & ((\|(4'...	Covered	T12,T63,T60
50 (addr_hit[49] & ((\|(4'...	Covered	T12,T63,T60
49 (addr_hit[48] & ((\|(4'...	Covered	T12,T63,T64
48 (addr_hit[47] & ((\|(4'...	Covered	T12,T63,T60
47 (addr_hit[46] & ((\|(4'...	Covered	T12,T63,T60
46 (addr_hit[45] & ((\|(4'...	Covered	T12,T63,T60
45 (addr_hit[44] & ((\|(4'...	Covered	T12,T63,T64
44 (addr_hit[43] & ((\|(4'...	Covered	T12,T63,T64
43 (addr_hit[42] & ((\|(4'...	Covered	T12,T63,T64
42 (addr_hit[41] & ((\|(4'...	Covered	T12,T63,T64
41 (addr_hit[40] & ((\|(4'...	Covered	T12,T63,T60
40 (addr_hit[39] & ((\|(4'...	Covered	T12,T63,T60
39 (addr_hit[38] & ((\|(4'...	Covered	T12,T63,T60
38 (addr_hit[37] & ((\|(4'...	Covered	T12,T63,T60
37 (addr_hit[36] & ((\|(4'...	Covered	T12,T63,T60
36 (addr_hit[35] & ((\|(4'...	Covered	T12,T63,T64
35 (addr_hit[34] & ((\|(4'...	Covered	T12,T63,T60
34 (addr_hit[33] & ((\|(4'...	Covered	T12,T63,T64
33 (addr_hit[32] & ((\|(4'...	Covered	T12,T63,T64
32 (addr_hit[31] & ((\|(4'...	Covered	T12,T63,T64
31 (addr_hit[30] & ((\|(4'...	Covered	T12,T63,T64
30 (addr_hit[29] & ((\|(4'...	Covered	T12,T63,T60
29 (addr_hit[28] & ((\|(4'...	Covered	T12,T63,T60
28 (addr_hit[27] & ((\|(4'...	Covered	T12,T63,T64
27 (addr_hit[26] & ((\|(4'...	Covered	T12,T63,T64
26 (addr_hit[25] & ((\|(4'...	Covered	T12,T63,T64
25 (addr_hit[24] & ((\|(4'...	Covered	T12,T63,T60
24 (addr_hit[23] & ((\|(4'...	Covered	T12,T63,T60
23 (addr_hit[22] & ((\|(4'...	Covered	T12,T63,T60
22 (addr_hit[21] & ((\|(4'...	Covered	T12,T63,T64
21 (addr_hit[20] & ((\|(4'...	Covered	T12,T63,T64
20 (addr_hit[19] & ((\|(4'...	Covered	T12,T63,T64
19 (addr_hit[18] & ((\|(4'...	Covered	T12,T63,T64
18 (addr_hit[17] & ((\|(4'...	Covered	T12,T63,T64
17 (addr_hit[16] & ((\|(4'...	Covered	T12,T63,T60
16 (addr_hit[15] & ((\|(4'...	Covered	T12,T63,T60
15 (addr_hit[14] & ((\|(4'...	Covered	T12,T63,T64
14 (addr_hit[13] & ((\|(4'...	Covered	T12,T63,T60
13 (addr_hit[12] & ((\|(4'...	Covered	T12,T63,T60
12 (addr_hit[11] & ((\|(4'...	Covered	T12,T63,T64
11 (addr_hit[10] & ((\|(4'...	Covered	T12,T63,T60
10 (addr_hit[9] & ((\|(4'b...	Covered	T12,T63,T60
9 (addr_hit[8] & ((\|(4'b...	Covered	T12,T63,T60
8 (addr_hit[7] & ((\|(4'b...	Covered	T12,T63,T60
7 (addr_hit[6] & ((\|(4'b...	Covered	T12,T63,T60
6 (addr_hit[5] & ((\|(4'b...	Covered	T12,T63,T60
5 (addr_hit[4] & ((\|(4'b...	Covered	T12,T63,T64
4 (addr_hit[3] & ((\|(4'b...	Covered	T12,T63,T60
3 (addr_hit[2] & ((\|(4'b...	Covered	T12,T23,T63
2 (addr_hit[1] & ((\|(4'b...	Covered	T12,T23,T63
1 (addr_hit[0] & ((\|(4'b...	Covered	T12,T22,T23

 LINE       11942
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T23,T63
1	0	Covered	T12,T23,T63
1	1	Covered	T12,T22,T23

 LINE       11942
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T23,T63

 LINE       11942
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T23,T63

 LINE       11942
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T60
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T64
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T23,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T60
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T64
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T60
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T63,T64,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T23
1	1	Covered	T12,T63,T60

 LINE       11942
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T63
1	1	Covered	T12,T63,T64

 LINE       11942
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T23
1	0	Covered	T12,T22,T64
1	1	Covered	T63,T60,T67