Go back

 LINE       12847
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T22,T23
1	0	1	Covered	T12,T22,T63
1	1	0	Covered	T67,T150,T253
1	1	1	Not Covered

 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T22,T23
1	0	1	Covered	T12,T22,T63
1	1	0	Covered	T63,T144,T149
1	1	1	Covered	T12,T22,T60

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T22,T23
1	0	1	Covered	T12,T22,T63
1	1	0	Covered	T63,T144,T254
1	1	1	Covered	T12,T22,T60

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T22,T23
1	0	1	Covered	T12,T22,T63
1	1	0	Covered	T63,T67,T149
1	1	1	Covered	T12,T22,T60

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T22,T23
1	0	1	Covered	T12,T22,T63
1	1	0	Covered	T255
1	1	1	Covered	T12,T22,T60

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T12,T22,T23