Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343	1		T2	1		T7	8		T8	8
all_values[1]	343	1		T2	1		T7	8		T8	8
all_values[2]	343	1		T2	1		T7	8		T8	8
all_values[3]	343	1		T2	1		T7	8		T8	8
all_values[4]	343	1		T2	1		T7	8		T8	8
all_values[5]	343	1		T2	1		T7	8		T8	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1107	1		T2	6		T7	26		T8	18
auto[1]	951	1		T7	22		T8	30		T9	26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1280	1		T2	6		T7	29		T8	22
auto[1]	778	1		T7	19		T8	26		T9	23

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	114	1		T2	1		T7	3		T8	1
all_values[0]	auto[0]	auto[1]	81	1		T7	1		T8	2		T9	3
all_values[0]	auto[1]	auto[0]	92	1		T7	3		T8	1		T9	2
all_values[0]	auto[1]	auto[1]	56	1		T7	1		T8	4		T29	1
all_values[1]	auto[0]	auto[0]	117	1		T2	1		T7	3		T8	3
all_values[1]	auto[0]	auto[1]	70	1		T7	3		T8	3		T9	3
all_values[1]	auto[1]	auto[0]	94	1		T7	2		T9	1		T16	4
all_values[1]	auto[1]	auto[1]	62	1		T8	2		T9	1		T16	1
all_values[2]	auto[0]	auto[0]	138	1		T2	1		T7	2		T8	3
all_values[2]	auto[0]	auto[1]	54	1		T7	4		T8	2		T9	2
all_values[2]	auto[1]	auto[0]	87	1		T7	1		T8	3		T9	1
all_values[2]	auto[1]	auto[1]	64	1		T7	1		T9	4		T16	1
all_values[3]	auto[0]	auto[0]	118	1		T2	1		T7	2		T9	1
all_values[3]	auto[0]	auto[1]	52	1		T8	1		T9	2		T29	1
all_values[3]	auto[1]	auto[0]	108	1		T7	4		T8	4		T9	3
all_values[3]	auto[1]	auto[1]	65	1		T7	2		T8	3		T9	2
all_values[4]	auto[0]	auto[0]	116	1		T2	1		T7	2		T8	1
all_values[4]	auto[0]	auto[1]	54	1		T7	3		T16	2		T29	1
all_values[4]	auto[1]	auto[0]	93	1		T8	5		T9	4		T16	1
all_values[4]	auto[1]	auto[1]	80	1		T7	3		T8	2		T9	2
all_values[5]	auto[0]	auto[0]	117	1		T2	1		T7	3		T9	1
all_values[5]	auto[0]	auto[1]	76	1		T8	2		T9	1		T16	3
all_values[5]	auto[1]	auto[0]	86	1		T7	4		T8	1		T9	3
all_values[5]	auto[1]	auto[1]	64	1		T7	1		T8	5		T9	3