Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |