Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
5 |
1 |
16.67 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.default_region.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
5 |
1 |
16.67 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
1 |
5 |
83.33 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
1 |
5 |
83.33 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| false |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| false |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| false |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| true |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
5 |
1 |
16.67 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| others[0] |
0 |
1 |
1 |
| others[1] |
0 |
1 |
1 |
| others[2] |
0 |
1 |
1 |
| others[3] |
0 |
1 |
1 |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| false |
79 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
13 |
1 |
|
T7 |
1 |
|
T9 |
1 |
|
T89 |
1 |
| others[1] |
14 |
1 |
|
T16 |
1 |
|
T29 |
1 |
|
T12 |
1 |
| others[2] |
19 |
1 |
|
T57 |
1 |
|
T60 |
1 |
|
T18 |
1 |
| others[3] |
22 |
1 |
|
T8 |
1 |
|
T77 |
1 |
|
T59 |
1 |
| false |
11 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T8 |
1 |
|
T77 |
1 |
|
T59 |
1 |
| others[1] |
17 |
1 |
|
T9 |
1 |
|
T12 |
1 |
|
T89 |
1 |
| others[2] |
17 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T29 |
1 |
| others[3] |
28 |
1 |
|
T57 |
1 |
|
T21 |
1 |
|
T43 |
1 |
| false |
7 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T90 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T59 |
1 |
|
T89 |
1 |
|
T91 |
1 |
| others[1] |
16 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T57 |
1 |
| others[2] |
18 |
1 |
|
T7 |
1 |
|
T8 |
1 |
|
T19 |
1 |
| others[3] |
23 |
1 |
|
T2 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| false |
6 |
1 |
|
T18 |
1 |
|
T25 |
1 |
|
T92 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T12 |
1 |
|
T59 |
1 |
|
T21 |
1 |
| others[1] |
14 |
1 |
|
T2 |
1 |
|
T29 |
1 |
|
T89 |
1 |
| others[2] |
16 |
1 |
|
T1 |
1 |
|
T77 |
1 |
|
T57 |
1 |
| others[3] |
23 |
1 |
|
T7 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| false |
10 |
1 |
|
T8 |
1 |
|
T91 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9 |
1 |
|
T19 |
1 |
|
T24 |
1 |
|
T93 |
1 |
| others[1] |
18 |
1 |
|
T1 |
1 |
|
T59 |
1 |
|
T21 |
1 |
| others[2] |
22 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T60 |
1 |
| others[3] |
22 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| false |
8 |
1 |
|
T7 |
1 |
|
T29 |
1 |
|
T77 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T18 |
1 |
|
T90 |
1 |
|
T19 |
1 |
| others[1] |
14 |
1 |
|
T1 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| others[2] |
14 |
1 |
|
T7 |
1 |
|
T12 |
1 |
|
T59 |
1 |
| others[3] |
27 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T29 |
1 |
| false |
8 |
1 |
|
T77 |
1 |
|
T94 |
1 |
|
T95 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
13 |
1 |
|
T29 |
1 |
|
T60 |
1 |
|
T96 |
1 |
| others[1] |
15 |
1 |
|
T77 |
1 |
|
T20 |
1 |
|
T43 |
1 |
| others[2] |
13 |
1 |
|
T16 |
1 |
|
T12 |
1 |
|
T18 |
1 |
| others[3] |
33 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
| false |
5 |
1 |
|
T97 |
1 |
|
T98 |
1 |
|
T99 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
19 |
1 |
|
T9 |
1 |
|
T16 |
1 |
|
T21 |
1 |
| others[1] |
18 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T29 |
1 |
| others[2] |
11 |
1 |
|
T1 |
1 |
|
T36 |
1 |
|
T100 |
1 |
| others[3] |
22 |
1 |
|
T57 |
1 |
|
T59 |
1 |
|
T20 |
1 |
| false |
9 |
1 |
|
T7 |
1 |
|
T77 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
17 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| others[1] |
19 |
1 |
|
T8 |
1 |
|
T16 |
1 |
|
T20 |
1 |
| others[2] |
8 |
1 |
|
T77 |
1 |
|
T59 |
1 |
|
T89 |
1 |
| others[3] |
27 |
1 |
|
T57 |
1 |
|
T21 |
1 |
|
T18 |
1 |
| false |
8 |
1 |
|
T2 |
1 |
|
T29 |
1 |
|
T60 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
13 |
1 |
|
T7 |
1 |
|
T77 |
1 |
|
T57 |
1 |
| others[1] |
16 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T97 |
1 |
| others[2] |
16 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T29 |
1 |
| others[3] |
25 |
1 |
|
T12 |
1 |
|
T59 |
1 |
|
T60 |
1 |
| false |
9 |
1 |
|
T9 |
1 |
|
T16 |
1 |
|
T90 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
17 |
1 |
|
T17 |
1 |
|
T90 |
1 |
|
T19 |
1 |
| others[1] |
19 |
1 |
|
T29 |
1 |
|
T77 |
1 |
|
T59 |
1 |
| others[2] |
12 |
1 |
|
T16 |
1 |
|
T43 |
1 |
|
T95 |
1 |
| others[3] |
21 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T8 |
1 |
| false |
10 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T60 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
20 |
1 |
|
T9 |
1 |
|
T20 |
1 |
|
T89 |
1 |
| others[1] |
16 |
1 |
|
T16 |
1 |
|
T29 |
1 |
|
T12 |
1 |
| others[2] |
19 |
1 |
|
T8 |
1 |
|
T59 |
1 |
|
T17 |
1 |
| others[3] |
22 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
| false |
2 |
1 |
|
T21 |
1 |
|
T101 |
1 |
|
- |
- |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
13 |
1 |
|
T29 |
1 |
|
T12 |
1 |
|
T21 |
1 |
| others[1] |
12 |
1 |
|
T60 |
1 |
|
T43 |
1 |
|
T102 |
1 |
| others[2] |
17 |
1 |
|
T9 |
1 |
|
T16 |
1 |
|
T77 |
1 |
| others[3] |
24 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
| false |
13 |
1 |
|
T8 |
1 |
|
T57 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
12 |
1 |
|
T9 |
1 |
|
T77 |
1 |
|
T57 |
1 |
| others[1] |
17 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T102 |
1 |
| others[2] |
10 |
1 |
|
T29 |
1 |
|
T20 |
1 |
|
T95 |
1 |
| others[3] |
34 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T16 |
1 |
| false |
6 |
1 |
|
T24 |
1 |
|
T25 |
1 |
|
T99 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
15 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T9 |
1 |
| others[1] |
15 |
1 |
|
T57 |
1 |
|
T90 |
1 |
|
T19 |
1 |
| others[2] |
18 |
1 |
|
T7 |
1 |
|
T89 |
1 |
|
T102 |
1 |
| others[3] |
23 |
1 |
|
T16 |
1 |
|
T29 |
1 |
|
T12 |
1 |
| false |
8 |
1 |
|
T2 |
1 |
|
T60 |
1 |
|
T43 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11 |
1 |
|
T16 |
1 |
|
T29 |
1 |
|
T43 |
1 |
| others[1] |
18 |
1 |
|
T77 |
1 |
|
T57 |
1 |
|
T21 |
1 |
| others[2] |
18 |
1 |
|
T9 |
1 |
|
T59 |
1 |
|
T60 |
1 |
| others[3] |
21 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
| false |
11 |
1 |
|
T20 |
1 |
|
T19 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T17 |
1 |
| others[1] |
7 |
1 |
|
T7 |
1 |
|
T77 |
1 |
|
T20 |
1 |
| others[2] |
16 |
1 |
|
T9 |
1 |
|
T16 |
1 |
|
T96 |
1 |
| others[3] |
30 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T59 |
1 |
| false |
10 |
1 |
|
T8 |
1 |
|
T57 |
1 |
|
T21 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
14 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
1 |
| others[1] |
14 |
1 |
|
T57 |
1 |
|
T60 |
1 |
|
T18 |
1 |
| others[2] |
15 |
1 |
|
T21 |
1 |
|
T43 |
1 |
|
T96 |
1 |
| others[3] |
28 |
1 |
|
T7 |
1 |
|
T8 |
1 |
|
T16 |
1 |
| false |
8 |
1 |
|
T9 |
1 |
|
T77 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T8 |
1 |
|
T21 |
1 |
|
T43 |
1 |
| others[1] |
12 |
1 |
|
T1 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| others[2] |
17 |
1 |
|
T7 |
1 |
|
T20 |
1 |
|
T90 |
1 |
| others[3] |
22 |
1 |
|
T2 |
1 |
|
T29 |
1 |
|
T77 |
1 |
| false |
12 |
1 |
|
T60 |
1 |
|
T91 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T59 |
1 |
|
T23 |
1 |
|
T103 |
1 |
| others[1] |
17 |
1 |
|
T9 |
1 |
|
T29 |
1 |
|
T57 |
1 |
| others[2] |
20 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T16 |
1 |
| others[3] |
25 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T77 |
1 |
| false |
7 |
1 |
|
T102 |
1 |
|
T28 |
1 |
|
T104 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
20 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T9 |
1 |
| others[1] |
15 |
1 |
|
T16 |
1 |
|
T60 |
1 |
|
T17 |
1 |
| others[2] |
10 |
1 |
|
T20 |
1 |
|
T105 |
1 |
|
T106 |
1 |
| others[3] |
25 |
1 |
|
T8 |
1 |
|
T12 |
1 |
|
T59 |
1 |
| false |
9 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T57 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
16 |
1 |
|
T12 |
1 |
|
T20 |
1 |
|
T18 |
1 |
| others[1] |
14 |
1 |
|
T1 |
1 |
|
T9 |
1 |
|
T77 |
1 |
| others[2] |
17 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T16 |
1 |
| others[3] |
25 |
1 |
|
T7 |
1 |
|
T43 |
1 |
|
T17 |
1 |
| false |
7 |
1 |
|
T24 |
1 |
|
T40 |
1 |
|
T47 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
15 |
1 |
|
T29 |
1 |
|
T96 |
1 |
|
T23 |
1 |
| others[1] |
17 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T9 |
1 |
| others[2] |
16 |
1 |
|
T17 |
1 |
|
T25 |
1 |
|
T36 |
1 |
| others[3] |
28 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T16 |
1 |
| false |
3 |
1 |
|
T60 |
1 |
|
T104 |
1 |
|
T107 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
18 |
1 |
|
T1 |
1 |
|
T59 |
1 |
|
T21 |
1 |
| others[1] |
16 |
1 |
|
T57 |
1 |
|
T17 |
1 |
|
T89 |
1 |
| others[2] |
12 |
1 |
|
T2 |
1 |
|
T7 |
1 |
|
T8 |
1 |
| others[3] |
26 |
1 |
|
T9 |
1 |
|
T16 |
1 |
|
T29 |
1 |
| false |
7 |
1 |
|
T20 |
1 |
|
T93 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
18 |
1 |
|
T16 |
1 |
|
T77 |
1 |
|
T21 |
1 |
| others[1] |
12 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T9 |
1 |
| others[2] |
14 |
1 |
|
T29 |
1 |
|
T57 |
1 |
|
T59 |
1 |
| others[3] |
25 |
1 |
|
T7 |
1 |
|
T8 |
1 |
|
T60 |
1 |
| false |
10 |
1 |
|
T12 |
1 |
|
T18 |
1 |
|
T102 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
12 |
1 |
|
T29 |
1 |
|
T57 |
1 |
|
T43 |
1 |
| others[1] |
17 |
1 |
|
T59 |
1 |
|
T21 |
1 |
|
T96 |
1 |
| others[2] |
17 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T60 |
1 |
| others[3] |
24 |
1 |
|
T7 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| false |
9 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T90 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
1 |
5 |
83.33 |
User Defined Bins for cp_value
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER |
| true |
0 |
1 |
1 |
Covered bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
12 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T21 |
1 |
| others[1] |
16 |
1 |
|
T2 |
1 |
|
T29 |
1 |
|
T18 |
1 |
| others[2] |
15 |
1 |
|
T8 |
1 |
|
T9 |
1 |
|
T59 |
1 |
| others[3] |
30 |
1 |
|
T16 |
1 |
|
T77 |
1 |
|
T12 |
1 |
| false |
6 |
1 |
|
T19 |
1 |
|
T108 |
1 |
|
T98 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |