Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343	1		T2	1		T7	8		T8	8
all_pins[1]	343	1		T2	1		T7	8		T8	8
all_pins[2]	343	1		T2	1		T7	8		T8	8
all_pins[3]	343	1		T2	1		T7	8		T8	8
all_pins[4]	343	1		T2	1		T7	8		T8	8
all_pins[5]	343	1		T2	1		T7	8		T8	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1667	1		T2	6		T7	40		T8	32
values[0x1]	391	1		T7	8		T8	16		T9	12
transitions[0x0=>0x1]	280	1		T7	6		T8	9		T9	7
transitions[0x1=>0x0]	294	1		T7	7		T8	10		T9	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	287	1		T2	1		T7	7		T8	4
all_pins[0]	values[0x1]	56	1		T7	1		T8	4		T29	1
all_pins[0]	transitions[0x0=>0x1]	44	1		T7	1		T8	3		T29	1
all_pins[0]	transitions[0x1=>0x0]	50	1		T8	1		T9	1		T16	1
all_pins[1]	values[0x0]	281	1		T2	1		T7	8		T8	6
all_pins[1]	values[0x1]	62	1		T8	2		T9	1		T16	1
all_pins[1]	transitions[0x0=>0x1]	43	1		T8	2		T77	1		T57	1
all_pins[1]	transitions[0x1=>0x0]	45	1		T7	1		T9	3		T77	1
all_pins[2]	values[0x0]	279	1		T2	1		T7	7		T8	8
all_pins[2]	values[0x1]	64	1		T7	1		T9	4		T16	1
all_pins[2]	transitions[0x0=>0x1]	43	1		T7	1		T9	4		T16	1
all_pins[2]	transitions[0x1=>0x0]	44	1		T7	2		T8	3		T9	2
all_pins[3]	values[0x0]	278	1		T2	1		T7	6		T8	5
all_pins[3]	values[0x1]	65	1		T7	2		T8	3		T9	2
all_pins[3]	transitions[0x0=>0x1]	47	1		T7	2		T8	2		T16	1
all_pins[3]	transitions[0x1=>0x0]	62	1		T7	3		T8	1		T77	1
all_pins[4]	values[0x0]	263	1		T2	1		T7	5		T8	6
all_pins[4]	values[0x1]	80	1		T7	3		T8	2		T9	2
all_pins[4]	transitions[0x0=>0x1]	64	1		T7	2		T16	1		T77	1
all_pins[4]	transitions[0x1=>0x0]	48	1		T8	3		T9	1		T16	2
all_pins[5]	values[0x0]	279	1		T2	1		T7	7		T8	3
all_pins[5]	values[0x1]	64	1		T7	1		T8	5		T9	3
all_pins[5]	transitions[0x0=>0x1]	39	1		T8	2		T9	3		T16	2
all_pins[5]	transitions[0x1=>0x0]	45	1		T7	1		T8	2		T29	1