Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	277	1		T7	7		T8	7		T9	7
all_values[1]	277	1		T7	7		T8	7		T9	7
all_values[2]	277	1		T7	7		T8	7		T9	7
all_values[3]	277	1		T7	7		T8	7		T9	7
all_values[4]	277	1		T7	7		T8	7		T9	7
all_values[5]	277	1		T7	7		T8	7		T9	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	887	1		T7	23		T8	16		T9	22
auto[1]	775	1		T7	19		T8	26		T9	20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	677	1		T7	20		T8	11		T9	16
auto[1]	985	1		T7	22		T8	31		T9	26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	992	1		T7	27		T8	21		T9	23
auto[1]	670	1		T7	15		T8	21		T9	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	56	1		T7	2		T9	2		T16	1
all_values[0]	auto[0]	auto[0]	auto[1]	34	1		T8	2		T9	1		T16	1
all_values[0]	auto[0]	auto[1]	auto[0]	46	1		T7	3		T9	2		T29	2
all_values[0]	auto[0]	auto[1]	auto[1]	25	1		T8	1		T29	1		T77	1
all_values[0]	auto[1]	auto[0]	auto[1]	67	1		T7	1		T8	1		T9	1
all_values[0]	auto[1]	auto[1]	auto[1]	49	1		T7	1		T8	3		T9	1
all_values[1]	auto[0]	auto[0]	auto[0]	57	1		T7	3		T8	2		T9	3
all_values[1]	auto[0]	auto[0]	auto[1]	31	1		T7	1		T8	1		T60	1
all_values[1]	auto[0]	auto[1]	auto[0]	58	1		T7	1		T16	3		T77	2
all_values[1]	auto[0]	auto[1]	auto[1]	20	1		T29	2		T57	1		T60	1
all_values[1]	auto[1]	auto[0]	auto[1]	58	1		T7	1		T8	3		T9	3
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T7	1		T8	1		T9	1
all_values[2]	auto[0]	auto[0]	auto[0]	72	1		T7	1		T8	1		T29	2
all_values[2]	auto[0]	auto[0]	auto[1]	24	1		T7	2		T9	1		T16	2
all_values[2]	auto[0]	auto[1]	auto[0]	47	1		T8	2		T16	1		T77	1
all_values[2]	auto[0]	auto[1]	auto[1]	20	1		T9	2		T29	1		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	57	1		T7	2		T8	3		T9	2
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T7	2		T8	1		T9	2
all_values[3]	auto[0]	auto[0]	auto[0]	62	1		T7	2		T9	2		T16	3
all_values[3]	auto[0]	auto[0]	auto[1]	14	1		T77	1		T57	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[0]	56	1		T7	2		T8	2		T16	1
all_values[3]	auto[0]	auto[1]	auto[1]	25	1		T7	1		T8	2		T9	1
all_values[3]	auto[1]	auto[0]	auto[1]	66	1		T7	1		T8	1		T9	2
all_values[3]	auto[1]	auto[1]	auto[1]	54	1		T7	1		T8	2		T9	2
all_values[4]	auto[0]	auto[0]	auto[0]	62	1		T7	1		T8	1		T9	1
all_values[4]	auto[0]	auto[0]	auto[1]	29	1		T7	1		T16	2		T43	1
all_values[4]	auto[0]	auto[1]	auto[0]	51	1		T8	3		T9	3		T29	1
all_values[4]	auto[0]	auto[1]	auto[1]	35	1		T7	1		T8	1		T9	1
all_values[4]	auto[1]	auto[0]	auto[1]	46	1		T7	1		T29	1		T77	4
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T7	3		T8	2		T9	2
all_values[5]	auto[0]	auto[0]	auto[0]	54	1		T7	3		T9	2		T29	1
all_values[5]	auto[0]	auto[0]	auto[1]	36	1		T16	1		T60	1		T43	2
all_values[5]	auto[0]	auto[1]	auto[0]	56	1		T7	2		T9	1		T16	1
all_values[5]	auto[0]	auto[1]	auto[1]	22	1		T7	1		T8	3		T9	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T7	1		T8	1		T9	2
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T8	3		T9	1		T16	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal