Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	231872	1		T1	60		T2	895		T3	57
full_word	173534	1		T1	86		T2	224		T10	1173

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	405126	1		T1	146		T2	1119		T3	57
auto[TlIntgErrCmd]	90	1		T5	12		T14	2		T31	3
auto[TlIntgErrData]	79	1		T5	4		T14	5		T31	3
auto[TlIntgErrBoth]	111	1		T5	4		T14	3		T31	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	269545	1		T1	58		T2	213		T3	57
auto[1]	135861	1		T1	88		T2	906		T10	584

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	177415	1		T1	57		T2	169		T3	57
auto[TlIntgErrNone]	partial	auto[1]	54199	1		T1	3		T2	726		T7	18
auto[TlIntgErrNone]	full_word	auto[0]	92012	1		T1	1		T2	44		T10	589
auto[TlIntgErrNone]	full_word	auto[1]	81500	1		T1	85		T2	180		T10	584
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T5	2		T31	1		T51	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T5	8		T14	2		T31	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T80	1		T82	1		T78	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T5	2		T31	1		T71	1
auto[TlIntgErrData]	partial	auto[0]	35	1		T5	1		T14	2		T31	1
auto[TlIntgErrData]	partial	auto[1]	39	1		T5	2		T14	3		T31	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T5	1		T82	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T53	1		T79	1		T78	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1		T5	2		T14	1		T31	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T5	2		T14	2		T31	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T31	1		T82	1		T53	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T79	1		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27792	1		T2	1522		T12	1252		T5	16
full_word	8250	1		T2	375		T12	574		T5	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35778	1		T2	1897		T12	1826		T17	947
auto[TlIntgErrCmd]	85	1		T5	6		T14	1		T31	3
auto[TlIntgErrData]	87	1		T5	5		T14	4		T31	5
auto[TlIntgErrBoth]	92	1		T5	8		T14	5		T31	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2058	1		T2	78		T12	108		T5	7
auto[1]	33984	1		T2	1819		T12	1718		T5	12

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1703	1		T2	69		T12	91		T17	38
auto[TlIntgErrNone]	partial	auto[1]	25849	1		T2	1453		T12	1161		T17	808
auto[TlIntgErrNone]	full_word	auto[0]	249	1		T2	9		T12	17		T17	6
auto[TlIntgErrNone]	full_word	auto[1]	7977	1		T2	366		T12	557		T17	95
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T5	2		T31	3		T51	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T5	2		T50	2		T80	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T5	1		T51	1		T53	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T5	1		T14	1		T83	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T5	2		T14	1		T31	3
auto[TlIntgErrData]	partial	auto[1]	33	1		T5	3		T14	2		T31	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T82	1		T85	1		T78	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T14	1		T82	1		T53	1
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T5	2		T14	1		T31	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T5	5		T14	2		T51	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T14	1		T82	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T5	1		T14	1		T83	1