| | | | | | | |
| gen_flash_cores[0].u_core |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_prog_data.u_prog |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_data_intg_chk |
0.00 |
0.00 |
|
0.00 |
|
|
|
| u_data_chk |
0.00 |
|
|
0.00 |
|
|
|
| u_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_plain_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_disable_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_erase |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_host_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_input_bufs[0].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[0].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[0].gen_fixed_arbiter.u_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_input_bufs[0].u_req_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[1].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[1].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[1].gen_fixed_arbiter.u_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_input_bufs[1].u_req_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_host_outstanding_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_rd |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_bufs[0].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_bufs[1].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_bufs[2].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_bufs[3].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_bus_intg |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_dec |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_intg_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_mask_storage |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_plain_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_rd_buf_dep |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rd_storage |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| u_rsp_order_fifo |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| u_valid_random |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_scramble |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_gf_mult.u_mult |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_prince.u_cipher |
0.00 |
|
|
0.00 |
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_flash_cores[0].u_host_rsp_fifo |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_flash_cores[1].u_core |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| gen_prog_data.u_prog |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_data_intg_chk |
0.00 |
0.00 |
|
0.00 |
|
|
|
| u_data_chk |
0.00 |
|
|
0.00 |
|
|
|
| u_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_plain_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_disable_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_erase |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_host_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_input_bufs[0].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[0].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[0].gen_fixed_arbiter.u_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_input_bufs[0].u_req_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[1].gen_data_bufs[0].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[1].gen_data_bufs[1].u_dat_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_input_bufs[1].gen_fixed_arbiter.u_arb |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_input_bufs[1].u_req_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_host_outstanding_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_rd |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_bufs[0].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_bufs[1].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_bufs[2].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_bufs[3].u_rd_buf |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_bus_intg |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_dec |
0.00 |
0.00 |
0.00 |
|
|
|
|
| u_intg_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_mask_storage |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_plain_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_rd_buf_dep |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rd_storage |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| u_rsp_order_fifo |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| u_valid_random |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_scramble |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_gf_mult.u_mult |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_prince.u_cipher |
0.00 |
|
|
0.00 |
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_flash_cores[1].u_host_rsp_fifo |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| u_bank_sequence_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_disable_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_flash |
67.76 |
66.36 |
76.62 |
88.69 |
0.00 |
74.92 |
100.00 |
| gen_generic.u_impl_generic |
67.76 |
66.36 |
76.62 |
88.69 |
0.00 |
74.92 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_lc_nvm_debug_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_region_sel |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|