| | | | | | | |
| flash_ctrl_core_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
| gen_alert_senders[0].u_alert_sender |
70.00 |
|
|
70.00 |
|
|
|
| gen_alert_senders[1].u_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_alert_senders[2].u_alert_sender |
70.00 |
|
|
70.00 |
|
|
|
| gen_alert_senders[3].u_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| gen_alert_senders[4].u_alert_sender |
77.78 |
|
|
77.78 |
|
|
|
| tlul_assert_device |
32.98 |
0.00 |
|
|
|
0.00 |
98.95 |
| u_ctrl_arb |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_disable_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[3].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[4].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[5].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[5].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[5].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[5].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[6].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[6].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[6].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[6].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[7].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[7].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[7].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[7].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_eflash |
33.82 |
26.67 |
20.77 |
18.83 |
0.00 |
36.67 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_exec_en_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_flash_ctrl_erase |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_flash_ctrl_prog |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| u_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_flash_ctrl_rd |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
0.00 |
|
| u_bus_intg |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_flash_hw_if |
8.45 |
0.00 |
0.00 |
42.26 |
0.00 |
0.00 |
|
| u_addr_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_addr_sync_reqack |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_nrz_hs_protocol.ack_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_nrz_hs_protocol.req_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_bus_intg |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_data_intg_chk |
44.38 |
0.00 |
|
88.75 |
|
|
|
| u_data_chk |
88.75 |
|
|
88.75 |
|
|
|
| u_data_sync_reqack |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_nrz_hs_protocol.ack_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_nrz_hs_protocol.req_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_page_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_prim_flop_err_sts |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_rma_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_seed_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_flash_init |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_rma_req |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[2].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_wipe_idx_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_word_cnt |
0.00 |
|
|
0.00 |
|
|
|
| u_flash_mp |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_hw_sel |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sw_sel |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_corr_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_op_done |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_prog_empty |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_prog_lvl |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_rd_full |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intr_rd_lvl |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_lc_escalation_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_lc_seed_hw_rd_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_lfsr |
0.00 |
|
|
0.00 |
|
|
|
| u_prog_empty_event |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prog_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_prog_lvl_event |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_prog_tl_gate |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| gen_lc_gating_muxes[0].u_prim_blanker_d2h |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[0].u_prim_blanker_h2d |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[1].u_prim_blanker_d2h |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[1].u_prim_blanker_h2d |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_err_en_sync |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul_err_resp |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intg_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_data_intg.u_tlul_data_integ_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rd_full_event |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_rd_lvl_event |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reg_core |
91.77 |
98.63 |
97.12 |
65.77 |
|
97.32 |
100.00 |
| subtree... |
|
|
|
|
|
|
|
| u_reg_idle |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_region_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_creator_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_owner_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_creator_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_owner_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_creator_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_owner_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_creator_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_owner_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_creator_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_owner_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_creator_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_owner_mubi |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_sec_buf.u_prim_sec_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_lc_creator_seed_sw_rw_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_lc_iso_part_sw_rd_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_lc_iso_part_sw_wr_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_lc_owner_seed_sw_rw_en_sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_flops.u_prim_flop_2sync |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_1 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sync_2 |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sw_rd_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tl_adapter_eflash |
25.00 |
0.00 |
0.00 |
100.00 |
|
0.00 |
|
| gen_cmd_intg_check.u_cmd_intg_chk |
50.00 |
0.00 |
|
100.00 |
|
|
|
| u_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_tlul_data_integ_dec |
50.00 |
0.00 |
|
100.00 |
|
|
|
| u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rspfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sram_byte |
0.00 |
0.00 |
|
|
|
|
|
| u_sramreqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tl_gate |
0.00 |
0.00 |
0.00 |
|
0.00 |
0.00 |
|
| gen_lc_gating_muxes[0].u_prim_blanker_d2h |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[0].u_prim_blanker_h2d |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[1].u_prim_blanker_d2h |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_lc_gating_muxes[1].u_prim_blanker_h2d |
0.00 |
0.00 |
|
|
|
|
|
| u_blank_and |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_err_en_sync |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[0].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[0].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[1].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[2].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| gen_buffs[1].gen_bits[3].u_prim_buf |
0.00 |
0.00 |
|
|
|
|
|
| u_secure_anchor_buf |
0.00 |
0.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
|
|
| u_state_regs |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_state_flop |
0.00 |
0.00 |
|
|
|
0.00 |
|
| gen_generic.u_impl_generic |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul_err_resp |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_intg_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_data_intg.u_tlul_data_integ_enc |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_to_prog_fifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rspfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_sram_byte |
0.00 |
0.00 |
|
|
|
|
|
| u_sramreqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_to_rd_fifo |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| u_err |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| u_reqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_rsp_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_rspfifo |
0.00 |
0.00 |
0.00 |
0.00 |
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
0.00 |
0.00 |
|
|
|
| gen_secure_ptrs.u_rptr |
0.00 |
|
|
0.00 |
|
|
|
| gen_secure_ptrs.u_wptr |
0.00 |
|
|
0.00 |
|
|
|
| u_sram_byte |
0.00 |
0.00 |
|
|
|
|
|
| u_sramreqfifo |
0.00 |
0.00 |
0.00 |
|
|
0.00 |
|
| gen_normal_fifo.u_fifo_cnt |
0.00 |
0.00 |
|
|
|
0.00 |
|
| u_tlul_data_integ_enc_data |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|
| u_tlul_data_integ_enc_instr |
0.00 |
0.00 |
|
|
|
|
|
| u_data_gen |
0.00 |
0.00 |
|
|
|
|
|