Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_phy_scramble
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble 0.00 0.00 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_gf_mult.u_mult 0.00 0.00 0.00 0.00
gen_prince.u_cipher 0.00 0.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 0.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_gf_mult.u_mult 0.00 0.00 0.00 0.00
gen_prince.u_cipher 0.00 0.00

Line Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
TOTAL1800.00
ALWAYS43400.00
CONT_ASSIGN50100.00
CONT_ASSIGN53100.00
CONT_ASSIGN89100.00
ALWAYS96400.00
ALWAYS112300.00
CONT_ASSIGN119100.00
CONT_ASSIGN120100.00
CONT_ASSIGN155100.00
CONT_ASSIGN158100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 0 1
45 0 1
46 0 1
==> MISSING_ELSE
50 0 1
53 0 1
89 0 1
96 0 1
97 0 1
98 0 1
99 0 1
==> MISSING_ELSE
112 0 1
113 0 1
115 0 1
119 0 1
120 0 1
155 0 1
158 0 1

Cond Coverage for Module : flash_phy_scramble
TotalCoveredPercent
Conditions2900.00
Logical2900.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Not Covered 

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Unreachable
10Not Covered
11Unreachable 

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Module : flash_phy_scramble
Line No.TotalCoveredPercent
Branches 20 0 0.00
TERNARY 50 2 0 0.00
TERNARY 119 2 0 0.00
TERNARY 155 2 0 0.00
TERNARY 158 2 0 0.00
TERNARY 132 2 0 0.00
TERNARY 132 2 0 0.00
IF 43 3 0 0.00
IF 96 3 0 0.00
IF 112 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	50	(addr_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	119	(op_ack_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	155	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	158	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	132	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	132	(data_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	112	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
Line No.TotalCoveredPercent
TOTAL1800.00
ALWAYS43400.00
CONT_ASSIGN50100.00
CONT_ASSIGN53100.00
CONT_ASSIGN89100.00
ALWAYS96400.00
ALWAYS112300.00
CONT_ASSIGN119100.00
CONT_ASSIGN120100.00
CONT_ASSIGN155100.00
CONT_ASSIGN158100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 0 1
45 0 1
46 0 1
==> MISSING_ELSE
50 0 1
53 0 1
89 0 1
96 0 1
97 0 1
98 0 1
99 0 1
==> MISSING_ELSE
112 0 1
113 0 1
115 0 1
119 0 1
120 0 1
155 0 1
158 0 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
TotalCoveredPercent
Conditions2900.00
Logical2900.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Not Covered 

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Unreachable
10Not Covered
11Unreachable 

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble
Line No.TotalCoveredPercent
Branches 20 0 0.00
TERNARY 50 2 0 0.00
TERNARY 119 2 0 0.00
TERNARY 155 2 0 0.00
TERNARY 158 2 0 0.00
TERNARY 132 2 0 0.00
TERNARY 132 2 0 0.00
IF 43 3 0 0.00
IF 96 3 0 0.00
IF 112 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	50	(addr_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	119	(op_ack_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	155	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	158	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	132	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	132	(data_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	112	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
Line No.TotalCoveredPercent
TOTAL1800.00
ALWAYS43400.00
CONT_ASSIGN50100.00
CONT_ASSIGN53100.00
CONT_ASSIGN89100.00
ALWAYS96400.00
ALWAYS112300.00
CONT_ASSIGN119100.00
CONT_ASSIGN120100.00
CONT_ASSIGN155100.00
CONT_ASSIGN158100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 0 1
44 0 1
45 0 1
46 0 1
==> MISSING_ELSE
50 0 1
53 0 1
89 0 1
96 0 1
97 0 1
98 0 1
99 0 1
==> MISSING_ELSE
112 0 1
113 0 1
115 0 1
119 0 1
120 0 1
155 0 1
158 0 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
TotalCoveredPercent
Conditions2900.00
Logical2900.00
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!calc_req_i)) || (calc_req_i && calc_ack_o))
             -------1-------    -------------2------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Not Covered 

 LINE       45
 SUB-EXPRESSION (calc_req_i && calc_ack_o)
                 -----1----    -----2----
-1--2-StatusTests
01Unreachable
10Not Covered
11Unreachable 

 LINE       50
 EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       89
 EXPRESSION (op_type_i == DeScrambleOp)
            -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       98
 EXPRESSION (((!op_req_i)) || (op_req_i && op_ack_o))
             ------1------    -----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       98
 SUB-EXPRESSION (op_req_i && op_ack_o)
                 ----1---    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       119
 EXPRESSION (op_ack_o ? '0 : (op_req_i & ((!cipher_valid_out))))
             ----1---
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       119
 SUB-EXPRESSION (op_req_i & ((!cipher_valid_out)))
                 ----1---   ----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       120
 EXPRESSION (cipher_valid_in_q & cipher_valid_out)
             --------1--------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       132
 EXPRESSION (dec ? scrambled_data_i : plain_data_i)
             -1-
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       132
 EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
             ------1-----
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       155
 EXPRESSION (dec ? data : scrambled_data_i)
             -1-
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       158
 EXPRESSION (dec ? plain_data_i : data)
             -1-
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble
Line No.TotalCoveredPercent
Branches 20 0 0.00
TERNARY 50 2 0 0.00
TERNARY 119 2 0 0.00
TERNARY 155 2 0 0.00
TERNARY 158 2 0 0.00
TERNARY 132 2 0 0.00
TERNARY 132 2 0 0.00
IF 43 3 0 0.00
IF 96 3 0 0.00
IF 112 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	50	(addr_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	119	(op_ack_o) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	155	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	158	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	132	(dec) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	132	(data_key_sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	45	if (((!calc_req_i) || (calc_req_i && calc_ack_o)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((!op_req_i) || (op_req_i && op_ack_o)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	112	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

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