Unified Coverage Report :: Module :: prim_generic_flash_bank

Module : prim_generic_flash_bank

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank	0.00	0.00	0.00		0.00	0.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	0.00	0.00				0.00
gen_info_types[1].u_info_mem	0.00	0.00				0.00
gen_info_types[2].u_info_mem	0.00	0.00				0.00
u_cmd_fifo	0.00	0.00	0.00			0.00
u_mem	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_info_types[0].u_info_mem	0.00	0.00				0.00
gen_info_types[1].u_info_mem	0.00	0.00				0.00
gen_info_types[2].u_info_mem	0.00	0.00				0.00
u_cmd_fifo	0.00	0.00	0.00			0.00
u_mem	0.00	0.00				0.00

Line Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	0	0.00
CONT_ASSIGN	127	1	0	0.00
CONT_ASSIGN	152	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	183	1	0	0.00
CONT_ASSIGN	184	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
ALWAYS	189	3	0	0.00
ALWAYS	194	9	0	0.00
ALWAYS	210	4	0	0.00
ALWAYS	221	6	0	0.00
CONT_ASSIGN	231	1	0	0.00
ALWAYS	236	13	0	0.00
ALWAYS	251	86	0	0.00
CONT_ASSIGN	402	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	446	1	0	0.00
CONT_ASSIGN	447	1	0	0.00
CONT_ASSIGN	450	1	0	0.00
CONT_ASSIGN	453	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	0	1
152	0	1
153	0	1
175	0	1
176	0	1
177	0	1
178	0	1
181	0	1
182	0	1
183	0	1
184	0	1
186	0	1
189	0	2
190	0	1
194	0	1
195	0	1
196	0	1
197	0	1
198	0	1
200	0	1
201	0	1
202	0	1
203	0	1
210	0	1
211	0	1
212	0	1
213	0	1
			==> MISSING_ELSE
221	0	1
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
231	0	1
236	0	1
237	0	1
238	0	1
240	0	2
241	0	2
242	0	2
			==> MISSING_ELSE
244	0	2
245	0	2
			==> MISSING_ELSE
251	0	1
254	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
260	0	1
261	0	1
262	0	1
263	0	1
264	0	1
267	0	1
268	0	1
269	0	1
271	0	1
273	0	1
274	0	1
275	0	1
			==> MISSING_ELSE
281	0	1
282	0	1
283	0	1
284	0	1
286	0	1
287	0	1
292	0	1
293	0	1
294	0	1
295	0	1
296	0	1
297	0	1
298	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305	0	1
306	0	1
307	0	1
308	0	1
			==> MISSING_ELSE
313	0	1
314	0	1
316	0	1
317	0	1
320	0	1
321	0	1
322	0	1
323	0	1
324	0	1
326	0	1
327	0	1
330	0	1
332	0	1
333	0	1
334	0	1
			==> MISSING_ELSE
340	0	1
341	0	1
342	0	1
343	0	1
344	0	1
346	0	1
347	0	1
348	0	1
349	0	1
355	0	1
356	0	1
357	0	1
358	0	1
359	0	1
360	0	1
361	0	1
362	0	1
364	0	1
365	0	1
366	0	1
367	0	1
368	0	1
375	0	1
376	0	1
377	0	1
378	0	1
379	0	1
390	0	1
391	0	1
			==> MISSING_ELSE
402	0	1
426	0	3
446	0	1
447	0	1
450	0	1
453	0	1

---

Cond Coverage for Module : prim_generic_flash_bank

	Total	Covered	Percent
Conditions	84	0	0.00
Logical	84	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : prim_generic_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	16	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Not Covered
StErase	302	Not Covered
StIdle	286	Not Covered
StInit	275	Not Covered
StProg	334	Not Covered
StRead	296	Not Covered
StReset	391	Not Covered

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Not Covered
StErSuspend->StReset	391	Not Covered
StErase->StErSuspend	356	Not Covered
StErase->StIdle	364	Not Covered
StErase->StReset	391	Not Covered
StIdle->StErase	302	Not Covered
StIdle->StRead	296	Not Covered
StIdle->StReset	391	Not Covered
StInit->StIdle	286	Not Covered
StInit->StReset	391	Not Covered
StProg->StIdle	346	Not Covered
StProg->StReset	391	Not Covered
StRead->StIdle	327	Not Covered
StRead->StProg	334	Not Covered
StRead->StReset	391	Not Covered
StReset->StInit	275	Not Covered

---

Branch Coverage for Module : prim_generic_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	0	0.00
TERNARY	231	2	0	0.00
TERNARY	447	2	0	0.00
IF	189	2	0	0.00
IF	194	2	0	0.00
IF	210	3	0	0.00
IF	221	3	0	0.00
IF	236	8	0	0.00
CASE	271	21	0	0.00
IF	390	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	231	((ReadLatency == 1)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	447	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	210	if ((!rst_ni))
-2-:	212	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	221	if ((!rst_ni))
-2-:	224	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	236	if ((!rst_ni))
-2-:	240	if (time_cnt_inc)
-3-:	241	if (time_cnt_set1)
-4-:	242	if (time_cnt_clr)
-5-:	244	if (index_cnt_inc)
-6-:	245	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Not Covered
0	0	0	0	-	-	Not Covered
0	-	-	-	1	-	Not Covered
0	-	-	-	0	1	Not Covered
0	-	-	-	0	0	Not Covered

	LineNo.	Expression
-1-:	271	case (st_q)
-2-:	274	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	282	if ((index_cnt < InitCycles))
-4-:	292	if (rd_req)
-5-:	297	if (prog_req)
-6-:	301	if (pg_erase_req)
-7-:	305	if (bk_erase_req)
-8-:	313	if ((time_cnt < ReadLatency))
-9-:	316	if ((!prog_pend_q))
-10-:	320	if (rd_req)
-11-:	330	if (prog_pend_q)
-12-:	341	if ((time_cnt < ProgLatency))
-13-:	355	if (erase_suspend_req_i)
-14-:	357	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	390	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	0	0.00
CONT_ASSIGN	127	1	0	0.00
CONT_ASSIGN	152	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	183	1	0	0.00
CONT_ASSIGN	184	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
ALWAYS	189	3	0	0.00
ALWAYS	194	9	0	0.00
ALWAYS	210	4	0	0.00
ALWAYS	221	6	0	0.00
CONT_ASSIGN	231	1	0	0.00
ALWAYS	236	13	0	0.00
ALWAYS	251	86	0	0.00
CONT_ASSIGN	402	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	446	1	0	0.00
CONT_ASSIGN	447	1	0	0.00
CONT_ASSIGN	450	1	0	0.00
CONT_ASSIGN	453	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	0	1
152	0	1
153	0	1
175	0	1
176	0	1
177	0	1
178	0	1
181	0	1
182	0	1
183	0	1
184	0	1
186	0	1
189	0	2
190	0	1
194	0	1
195	0	1
196	0	1
197	0	1
198	0	1
200	0	1
201	0	1
202	0	1
203	0	1
210	0	1
211	0	1
212	0	1
213	0	1
			==> MISSING_ELSE
221	0	1
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
231	0	1
236	0	1
237	0	1
238	0	1
240	0	2
241	0	2
242	0	2
			==> MISSING_ELSE
244	0	2
245	0	2
			==> MISSING_ELSE
251	0	1
254	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
260	0	1
261	0	1
262	0	1
263	0	1
264	0	1
267	0	1
268	0	1
269	0	1
271	0	1
273	0	1
274	0	1
275	0	1
			==> MISSING_ELSE
281	0	1
282	0	1
283	0	1
284	0	1
286	0	1
287	0	1
292	0	1
293	0	1
294	0	1
295	0	1
296	0	1
297	0	1
298	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305	0	1
306	0	1
307	0	1
308	0	1
			==> MISSING_ELSE
313	0	1
314	0	1
316	0	1
317	0	1
320	0	1
321	0	1
322	0	1
323	0	1
324	0	1
326	0	1
327	0	1
330	0	1
332	0	1
333	0	1
334	0	1
			==> MISSING_ELSE
340	0	1
341	0	1
342	0	1
343	0	1
344	0	1
346	0	1
347	0	1
348	0	1
349	0	1
355	0	1
356	0	1
357	0	1
358	0	1
359	0	1
360	0	1
361	0	1
362	0	1
364	0	1
365	0	1
366	0	1
367	0	1
368	0	1
375	0	1
376	0	1
377	0	1
378	0	1
379	0	1
390	0	1
391	0	1
			==> MISSING_ELSE
402	0	1
426	0	3
446	0	1
447	0	1
450	0	1
453	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Total	Covered	Percent
Conditions	84	0	0.00
Logical	84	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	16	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Not Covered
StErase	302	Not Covered
StIdle	286	Not Covered
StInit	275	Not Covered
StProg	334	Not Covered
StRead	296	Not Covered
StReset	391	Not Covered

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Not Covered
StErSuspend->StReset	391	Not Covered
StErase->StErSuspend	356	Not Covered
StErase->StIdle	364	Not Covered
StErase->StReset	391	Not Covered
StIdle->StErase	302	Not Covered
StIdle->StRead	296	Not Covered
StIdle->StReset	391	Not Covered
StInit->StIdle	286	Not Covered
StInit->StReset	391	Not Covered
StProg->StIdle	346	Not Covered
StProg->StReset	391	Not Covered
StRead->StIdle	327	Not Covered
StRead->StProg	334	Not Covered
StRead->StReset	391	Not Covered
StReset->StInit	275	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	0	0.00
TERNARY	231	2	0	0.00
TERNARY	447	2	0	0.00
IF	189	2	0	0.00
IF	194	2	0	0.00
IF	210	3	0	0.00
IF	221	3	0	0.00
IF	236	8	0	0.00
CASE	271	21	0	0.00
IF	390	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	231	((ReadLatency == 1)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	447	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	210	if ((!rst_ni))
-2-:	212	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	221	if ((!rst_ni))
-2-:	224	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	236	if ((!rst_ni))
-2-:	240	if (time_cnt_inc)
-3-:	241	if (time_cnt_set1)
-4-:	242	if (time_cnt_clr)
-5-:	244	if (index_cnt_inc)
-6-:	245	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Not Covered
0	0	0	0	-	-	Not Covered
0	-	-	-	1	-	Not Covered
0	-	-	-	0	1	Not Covered
0	-	-	-	0	0	Not Covered

	LineNo.	Expression
-1-:	271	case (st_q)
-2-:	274	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	282	if ((index_cnt < InitCycles))
-4-:	292	if (rd_req)
-5-:	297	if (prog_req)
-6-:	301	if (pg_erase_req)
-7-:	305	if (bk_erase_req)
-8-:	313	if ((time_cnt < ReadLatency))
-9-:	316	if ((!prog_pend_q))
-10-:	320	if (rd_req)
-11-:	330	if (prog_pend_q)
-12-:	341	if ((time_cnt < ProgLatency))
-13-:	355	if (erase_suspend_req_i)
-14-:	357	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	390	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
TOTAL		142	0	0.00
CONT_ASSIGN	127	1	0	0.00
CONT_ASSIGN	152	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	181	1	0	0.00
CONT_ASSIGN	182	1	0	0.00
CONT_ASSIGN	183	1	0	0.00
CONT_ASSIGN	184	1	0	0.00
CONT_ASSIGN	186	1	0	0.00
ALWAYS	189	3	0	0.00
ALWAYS	194	9	0	0.00
ALWAYS	210	4	0	0.00
ALWAYS	221	6	0	0.00
CONT_ASSIGN	231	1	0	0.00
ALWAYS	236	13	0	0.00
ALWAYS	251	86	0	0.00
CONT_ASSIGN	402	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	446	1	0	0.00
CONT_ASSIGN	447	1	0	0.00
CONT_ASSIGN	450	1	0	0.00
CONT_ASSIGN	453	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
127	0	1
152	0	1
153	0	1
175	0	1
176	0	1
177	0	1
178	0	1
181	0	1
182	0	1
183	0	1
184	0	1
186	0	1
189	0	2
190	0	1
194	0	1
195	0	1
196	0	1
197	0	1
198	0	1
200	0	1
201	0	1
202	0	1
203	0	1
210	0	1
211	0	1
212	0	1
213	0	1
			==> MISSING_ELSE
221	0	1
222	0	1
223	0	1
224	0	1
225	0	1
226	0	1
			==> MISSING_ELSE
231	0	1
236	0	1
237	0	1
238	0	1
240	0	2
241	0	2
242	0	2
			==> MISSING_ELSE
244	0	2
245	0	2
			==> MISSING_ELSE
251	0	1
254	0	1
255	0	1
256	0	1
257	0	1
258	0	1
259	0	1
260	0	1
261	0	1
262	0	1
263	0	1
264	0	1
267	0	1
268	0	1
269	0	1
271	0	1
273	0	1
274	0	1
275	0	1
			==> MISSING_ELSE
281	0	1
282	0	1
283	0	1
284	0	1
286	0	1
287	0	1
292	0	1
293	0	1
294	0	1
295	0	1
296	0	1
297	0	1
298	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305	0	1
306	0	1
307	0	1
308	0	1
			==> MISSING_ELSE
313	0	1
314	0	1
316	0	1
317	0	1
320	0	1
321	0	1
322	0	1
323	0	1
324	0	1
326	0	1
327	0	1
330	0	1
332	0	1
333	0	1
334	0	1
			==> MISSING_ELSE
340	0	1
341	0	1
342	0	1
343	0	1
344	0	1
346	0	1
347	0	1
348	0	1
349	0	1
355	0	1
356	0	1
357	0	1
358	0	1
359	0	1
360	0	1
361	0	1
362	0	1
364	0	1
365	0	1
366	0	1
367	0	1
368	0	1
375	0	1
376	0	1
377	0	1
378	0	1
379	0	1
390	0	1
391	0	1
			==> MISSING_ELSE
402	0	1
426	0	3
446	0	1
447	0	1
450	0	1
453	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Total	Covered	Percent
Conditions	84	0	0.00
Logical	84	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION ((rd_i | prog_i | pg_erase_i | bk_erase_i) & ((!init_busy_o)))
             --------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       152
 SUB-EXPRESSION (rd_i | prog_i | pg_erase_i | bk_erase_i)
                 --1-   ---2--   -----3----   -----4----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       153
 EXPRESSION (ack & ((!init_busy_o)))
             -1-   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       175
 EXPRESSION (cmd_valid & cmd_q.rd)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       176
 EXPRESSION (cmd_valid & cmd_q.prog)
             ----1----   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       177
 EXPRESSION (cmd_valid & cmd_q.pg_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       178
 EXPRESSION (cmd_valid & cmd_q.bk_erase)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       181
 EXPRESSION (mem_req & ((~mem_wr)))
             ---1---   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       231
 EXPRESSION ((ReadLatency == 1) ? rd_data_d : rd_data_q)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       231
 SUB-EXPRESSION (ReadLatency == 1)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       274
 EXPRESSION (init_i && flash_power_ready_h_i && ((!flash_power_down_h_i)))
             ---1--    ----------2----------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Unreachable
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       357
 EXPRESSION ((index_cnt < index_limit_q) || (time_cnt < time_limit_q))
             -------------1-------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       390
 EXPRESSION (((!flash_power_ready_h_i)) || flash_power_down_h_i)
             -------------1------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       402
 EXPRESSION (mem_req & ((mem_part == FlashPartData) | mem_bk_erase))
             ---1---   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       402
 SUB-EXPRESSION ((mem_part == FlashPartData) | mem_bk_erase)
                 -------------1-------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       402
 SUB-EXPRESSION (mem_part == FlashPartData)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 0) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 0) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 0)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 1) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 1) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 1)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (mem_req & (mem_part == FlashPartInfo) & ((mem_info_sel == 2) | mem_bk_erase))
             ---1---   -------------2-------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_part == FlashPartInfo)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 SUB-EXPRESSION ((mem_info_sel == 2) | mem_bk_erase)
                 ---------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       426
 SUB-EXPRESSION (mem_info_sel == 2)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 EXPRESSION ((rd_part_q == FlashPartData) ? rd_data_main : rd_data_info)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       447
 SUB-EXPRESSION (rd_part_q == FlashPartData)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	0	0.00	(Not included in score)
Transitions	16	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StErSuspend	356	Not Covered
StErase	302	Not Covered
StIdle	286	Not Covered
StInit	275	Not Covered
StProg	334	Not Covered
StRead	296	Not Covered
StReset	391	Not Covered

transitions	Line No.	Covered	Tests
StErSuspend->StIdle	379	Not Covered
StErSuspend->StReset	391	Not Covered
StErase->StErSuspend	356	Not Covered
StErase->StIdle	364	Not Covered
StErase->StReset	391	Not Covered
StIdle->StErase	302	Not Covered
StIdle->StRead	296	Not Covered
StIdle->StReset	391	Not Covered
StInit->StIdle	286	Not Covered
StInit->StReset	391	Not Covered
StProg->StIdle	346	Not Covered
StProg->StReset	391	Not Covered
StRead->StIdle	327	Not Covered
StRead->StProg	334	Not Covered
StRead->StReset	391	Not Covered
StReset->StInit	275	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank

	Line No.	Total	Covered	Percent
Branches		45	0	0.00
TERNARY	231	2	0	0.00
TERNARY	447	2	0	0.00
IF	189	2	0	0.00
IF	194	2	0	0.00
IF	210	3	0	0.00
IF	221	3	0	0.00
IF	236	8	0	0.00
CASE	271	21	0	0.00
IF	390	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash_bank.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	231	((ReadLatency == 1)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	447	((rd_part_q == FlashPartData)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	189	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	194	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	210	if ((!rst_ni))
-2-:	212	if (mem_rd_q)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	221	if ((!rst_ni))
-2-:	224	if (mem_rd_d)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	236	if ((!rst_ni))
-2-:	240	if (time_cnt_inc)
-3-:	241	if (time_cnt_set1)
-4-:	242	if (time_cnt_clr)
-5-:	244	if (index_cnt_inc)
-6-:	245	if (index_cnt_clr)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Not Covered
0	0	0	0	-	-	Not Covered
0	-	-	-	1	-	Not Covered
0	-	-	-	0	1	Not Covered
0	-	-	-	0	0	Not Covered

	LineNo.	Expression
-1-:	271	case (st_q)
-2-:	274	if (((init_i && flash_power_ready_h_i) && (!flash_power_down_h_i)))
-3-:	282	if ((index_cnt < InitCycles))
-4-:	292	if (rd_req)
-5-:	297	if (prog_req)
-6-:	301	if (pg_erase_req)
-7-:	305	if (bk_erase_req)
-8-:	313	if ((time_cnt < ReadLatency))
-9-:	316	if ((!prog_pend_q))
-10-:	320	if (rd_req)
-11-:	330	if (prog_pend_q)
-12-:	341	if ((time_cnt < ProgLatency))
-13-:	355	if (erase_suspend_req_i)
-14-:	357	if (((index_cnt < index_limit_q) || (time_cnt < time_limit_q)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StReset	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReset	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInit	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInit	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	1	-	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	0	1	-	-	-	-	-	-	-	Not Covered
StIdle	-	-	0	0	0	0	-	-	-	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	1	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	0	-	1	-	-	-	Not Covered
StRead	-	-	-	-	-	-	0	0	-	0	-	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StProg	-	-	-	-	-	-	-	-	-	-	0	-	-	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	0	1	Not Covered
StErase	-	-	-	-	-	-	-	-	-	-	-	0	0	Not Covered
StErSuspend	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	390	if (((!flash_power_ready_h_i) || flash_power_down_h_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered