Unified Coverage Report :: Module :: prim_lfsr

Module : prim_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lfsr_0.1/rtl/prim_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lfsr	0.00			0.00

---

Module Instance : tb.dut.u_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_lfsr

	Total	Covered	Percent
Totals	6	0	0.00
Total Bits	136	0	0.00
Total Bits 0->1	68	0	0.00
Total Bits 1->0	68	0	0.00

Ports	6	0	0.00
Port Bits	136	0	0.00
Port Bits 0->1	68	0	0.00
Port Bits 1->0	68	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
seed_en_i	No	No		No		INPUT
seed_i[31:0]	No	No		No		INPUT
lfsr_en_i	No	No		No		INPUT
entropy_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
state_o[31:0]	No	No		No		OUTPUT