Unified Coverage Report :: Module :: prim_generic_flash

Module : prim_generic_flash

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic	0.00	0.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.76	66.36	76.62	88.69	0.00	74.92	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_flash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_flash_banks[0].u_prim_flash_bank	0.00	0.00	0.00		0.00	0.00
gen_prim_flash_banks[1].u_prim_flash_bank	0.00	0.00	0.00		0.00	0.00
u_reg_top	96.63	99.31	95.61	88.69		99.56	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_flash

	Line No.	Total	Covered	Percent
TOTAL		10	0	0.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	56	1	0	0.00
CONT_ASSIGN	105	0	0
CONT_ASSIGN	106	0	0
CONT_ASSIGN	107	0	0
CONT_ASSIGN	108	1	0	0.00
CONT_ASSIGN	109	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	112	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	147	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash.sv' or '../src/lowrisc_prim_generic_flash_0/rtl/prim_generic_flash.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49		unreachable
56	0	1
105		unreachable
106		unreachable
107		unreachable
108	0	1
109	0	1
110	0	1
111	0	1
112	0	1
134	0	1
138	0	1
143	0	1
147	0	1