Unified Coverage Report :: Module :: prim_sparse_fsm_flop

Module : prim_sparse_fsm_flop

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl_arb.u_state_regs	0.00	0.00
tb.dut.u_flash_hw_if.u_state_regs	0.00	0.00
tb.dut.u_flash_hw_if.u_rma_state_regs	0.00	0.00
tb.dut.u_prog_tl_gate.u_state_regs	0.00	0.00
tb.dut.u_tl_gate.u_state_regs	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs	0.00	0.00

---

Module Instance : tb.dut.u_ctrl_arb.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_ctrl_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_flash_hw_if.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_flash_hw_if.u_rma_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_prog_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_tl_gate.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_prog_data.u_prog

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_flop	0.00	0.00				0.00

Line Coverage for Module : prim_sparse_fsm_flop

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_ctrl_arb.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_rma_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_tl_gate.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	40	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ROUTINE	47	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' or '../src/lowrisc_prim_sparse_fsm_0/rtl/prim_sparse_fsm_flop.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
40	0	1
43	0	1
47	0	1
48	0	1
49	0	1
51	0	1