Unified Coverage Report :: Cond split page

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 LINE       70
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T5
1	1	Covered	T1,T2,T10

 LINE       82
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T14,T31

 LINE       89
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T5,T14,T31
1	0	0	Covered	T5,T14,T31

 LINE       139
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[432:435]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[436:439]}) ? 2'b1 : 2'd2))
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       139
 SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[436:439]}) ? 2'b1 : 2'd2)
                 -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T4

 LINE       178
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T5,T14,T31
0	1	0	Covered	T2,T12,T17
1	0	0	Covered	T2,T12,T23

 LINE       178
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T5

 LINE       1642
 EXPRESSION (control_we & ctrl_regwen_qs)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T13,T4

 LINE       1836
 EXPRESSION (addr_we & ctrl_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T13,T4

 LINE       1867
 EXPRESSION (prog_type_en_we & ctrl_regwen_qs)
             -------1-------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T13,T4

 LINE       2187
 EXPRESSION (mp_region_cfg_0_we & region_cfg_regwen_0_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T11
1	1	Covered	T1,T2,T7

 LINE       2382
 EXPRESSION (mp_region_cfg_1_we & region_cfg_regwen_1_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T11
1	1	Covered	T1,T2,T10

 LINE       2577
 EXPRESSION (mp_region_cfg_2_we & region_cfg_regwen_2_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T1,T2,T7

 LINE       2772
 EXPRESSION (mp_region_cfg_3_we & region_cfg_regwen_3_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T15,T33
1	1	Covered	T1,T2,T10

 LINE       2967
 EXPRESSION (mp_region_cfg_4_we & region_cfg_regwen_4_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T5
1	1	Covered	T1,T2,T10

 LINE       3162
 EXPRESSION (mp_region_cfg_5_we & region_cfg_regwen_5_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T5,T15
1	1	Covered	T1,T2,T10

 LINE       3357
 EXPRESSION (mp_region_cfg_6_we & region_cfg_regwen_6_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T4,T5
1	1	Covered	T1,T2,T7

 LINE       3552
 EXPRESSION (mp_region_cfg_7_we & region_cfg_regwen_7_qs)
             ---------1--------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T11
1	1	Covered	T1,T2,T10

 LINE       3747
 EXPRESSION (mp_region_0_we & region_cfg_regwen_0_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T4,T11
1	1	Covered	T1,T2,T7

 LINE       3807
 EXPRESSION (mp_region_1_we & region_cfg_regwen_1_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T15
1	1	Covered	T1,T2,T10

 LINE       3867
 EXPRESSION (mp_region_2_we & region_cfg_regwen_2_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T4,T5
1	1	Covered	T1,T2,T7

 LINE       3927
 EXPRESSION (mp_region_3_we & region_cfg_regwen_3_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T15,T32
1	1	Covered	T1,T2,T10

 LINE       3987
 EXPRESSION (mp_region_4_we & region_cfg_regwen_4_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T5
1	1	Covered	T1,T2,T10

 LINE       4047
 EXPRESSION (mp_region_5_we & region_cfg_regwen_5_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T5,T15
1	1	Covered	T1,T2,T7

 LINE       4107
 EXPRESSION (mp_region_6_we & region_cfg_regwen_6_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T1,T2,T7

 LINE       4167
 EXPRESSION (mp_region_7_we & region_cfg_regwen_7_qs)
             -------1------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T5
1	1	Covered	T1,T2,T10

 LINE       4681
 EXPRESSION (bank0_info0_page_cfg_0_we & bank0_info0_regwen_0_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T14
1	1	Covered	T1,T2,T10

 LINE       4876
 EXPRESSION (bank0_info0_page_cfg_1_we & bank0_info0_regwen_1_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T4,T5
1	1	Covered	T1,T2,T7

 LINE       5071
 EXPRESSION (bank0_info0_page_cfg_2_we & bank0_info0_regwen_2_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T11
1	1	Covered	T1,T2,T10

 LINE       5266
 EXPRESSION (bank0_info0_page_cfg_3_we & bank0_info0_regwen_3_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T1,T2,T7

 LINE       5461
 EXPRESSION (bank0_info0_page_cfg_4_we & bank0_info0_regwen_4_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T5
1	1	Covered	T1,T2,T10

 LINE       5656
 EXPRESSION (bank0_info0_page_cfg_5_we & bank0_info0_regwen_5_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T5,T15
1	1	Covered	T1,T2,T7

 LINE       5851
 EXPRESSION (bank0_info0_page_cfg_6_we & bank0_info0_regwen_6_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T32
1	1	Covered	T1,T2,T10

 LINE       6046
 EXPRESSION (bank0_info0_page_cfg_7_we & bank0_info0_regwen_7_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T15
1	1	Covered	T1,T2,T10

 LINE       6241
 EXPRESSION (bank0_info0_page_cfg_8_we & bank0_info0_regwen_8_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T33
1	1	Covered	T1,T2,T10

 LINE       6436
 EXPRESSION (bank0_info0_page_cfg_9_we & bank0_info0_regwen_9_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T11
1	1	Covered	T1,T2,T10

 LINE       6660
 EXPRESSION (bank0_info1_page_cfg_we & bank0_info1_regwen_qs)
             -----------1-----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T5
1	1	Covered	T1,T2,T10

 LINE       6913
 EXPRESSION (bank0_info2_page_cfg_0_we & bank0_info2_regwen_0_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T5,T15
1	1	Covered	T1,T2,T10

 LINE       7108
 EXPRESSION (bank0_info2_page_cfg_1_we & bank0_info2_regwen_1_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T4,T5
1	1	Covered	T1,T2,T7

 LINE       7593
 EXPRESSION (bank1_info0_page_cfg_0_we & bank1_info0_regwen_0_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T1,T2,T7

 LINE       7788
 EXPRESSION (bank1_info0_page_cfg_1_we & bank1_info0_regwen_1_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T33
1	1	Covered	T1,T2,T10

 LINE       7983
 EXPRESSION (bank1_info0_page_cfg_2_we & bank1_info0_regwen_2_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T5
1	1	Covered	T1,T2,T10

 LINE       8178
 EXPRESSION (bank1_info0_page_cfg_3_we & bank1_info0_regwen_3_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T15
1	1	Covered	T1,T2,T7

 LINE       8373
 EXPRESSION (bank1_info0_page_cfg_4_we & bank1_info0_regwen_4_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T15
1	1	Covered	T1,T2,T10

 LINE       8568
 EXPRESSION (bank1_info0_page_cfg_5_we & bank1_info0_regwen_5_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T5
1	1	Covered	T1,T2,T10

 LINE       8763
 EXPRESSION (bank1_info0_page_cfg_6_we & bank1_info0_regwen_6_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T15,T32
1	1	Covered	T1,T2,T10

 LINE       8958
 EXPRESSION (bank1_info0_page_cfg_7_we & bank1_info0_regwen_7_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T15,T32
1	1	Covered	T1,T2,T10

 LINE       9153
 EXPRESSION (bank1_info0_page_cfg_8_we & bank1_info0_regwen_8_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T5,T32
1	1	Covered	T1,T2,T7

 LINE       9348
 EXPRESSION (bank1_info0_page_cfg_9_we & bank1_info0_regwen_9_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T11,T5
1	1	Covered	T1,T2,T10

 LINE       9572
 EXPRESSION (bank1_info1_page_cfg_we & bank1_info1_regwen_qs)
             -----------1-----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T4,T5
1	1	Covered	T1,T2,T10

 LINE       9825
 EXPRESSION (bank1_info2_page_cfg_0_we & bank1_info2_regwen_0_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T1,T2,T7

 LINE       10020
 EXPRESSION (bank1_info2_page_cfg_1_we & bank1_info2_regwen_1_qs)
             ------------1------------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T15
1	1	Covered	T1,T2,T10

 LINE       10299
 EXPRESSION (mp_bank_cfg_shadowed_we & bank_cfg_regwen_qs)
             -----------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T5,T15,T6

 LINE       11828
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       11829
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T7

 LINE       11830
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T7

 LINE       11831
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11832
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11833
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11834
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11835
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11836
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11837
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11838
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11839
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11840
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11841
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11842
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11843
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11844
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11845
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11846
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11847
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11848
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11849
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11850
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11851
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11852
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_4_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11853
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_5_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11854
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_6_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11855
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_7_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11856
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_0_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11857
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_1_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11858
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_2_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11859
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_3_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11860
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_4_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11861
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_5_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11862
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_6_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11863
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_7_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11864
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11865
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11866
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11867
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11868
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11869
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11870
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11871
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11872
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11873
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11874
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11875
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11876
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11877
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11878
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11879
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11880
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11881
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11882
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11883
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11884
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11885
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11886
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11887
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11888
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11889
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11890
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11891
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11892
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11893
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11894
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11895
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11896
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11897
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11898
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11899
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11900
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11901
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11902
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11903
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11904
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11905
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11906
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11907
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11908
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11909
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11910
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11911
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11912
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11913
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11914
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11915
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11916
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T10

 LINE       11917
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11918
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK_CFG_REGWEN_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11919
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11920
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_OP_STATUS_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11921
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_STATUS_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       11922
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_DEBUG_STATE_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11923
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ERR_CODE_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11924
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_STD_FAULT_STATUS_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11925
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_FAULT_STATUS_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11926
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ERR_ADDR_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11927
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET)
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11928
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11929
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11930
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_PHY_ALERT_CFG_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11931
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_PHY_STATUS_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11932
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_SCRATCH_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11933
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_LVL_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11934
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_FIFO_RST_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11935
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CURR_FIFO_LVL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T13

 LINE       11938
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       11938
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3

 LINE       11942
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[79] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[80] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[81] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[82] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | (addr_hit[84] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | (addr_hit[87] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[88] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | (addr_hit[94] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | (addr_hit[96] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[97] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[98] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[99] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[100] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[101] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | (addr_hit[104] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[105] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | (addr_hit[107] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T10
1	1	Covered	T2,T12,T17