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 LINE       11942
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T4
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       11942
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T13
1	1	Covered	T2,T10,T4

 LINE       12054
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T12,T24
1	1	1	Covered	T7,T8,T9

 LINE       12067
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T7
1	1	0	Covered	T25,T45,T46
1	1	1	Covered	T10,T7,T13

 LINE       12080
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T7
1	1	0	Covered	T17,T24,T47
1	1	1	Covered	T7,T8,T9

 LINE       12093
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T14
1	1	1	Covered	T10,T13,T4

 LINE       12104
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T25,T28
1	1	1	Not Covered

 LINE       12107
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12110
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T25,T45
1	1	1	Covered	T1,T2,T10

 LINE       12113
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T10,T13
1	1	0	Not Covered
1	1	1	Covered	T6,T34,T22

 LINE       12114
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T24,T25,T48
1	1	1	Covered	T10,T13,T4

 LINE       12129
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T25,T28,T30
1	1	1	Covered	T10,T13,T4

 LINE       12132
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T17
1	1	1	Covered	T10,T13,T4

 LINE       12137
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T24,T30
1	1	1	Not Covered

 LINE       12140
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T46,T47,T49
1	1	1	Covered	T10,T13,T4

 LINE       12143
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T25,T30
1	1	1	Covered	T10,T13,T4

 LINE       12146
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T17,T31
1	1	1	Covered	T10,T13,T4

 LINE       12149
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T24
1	1	1	Covered	T10,T13,T4

 LINE       12152
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T23,T24,T28
1	1	1	Covered	T10,T13,T4

 LINE       12155
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T23,T24,T30
1	1	1	Covered	T10,T13,T4

 LINE       12158
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T28,T50,T30
1	1	1	Covered	T10,T13,T4

 LINE       12161
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T23,T24
1	1	1	Covered	T10,T13,T4

 LINE       12164
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T25,T28,T30
1	1	1	Covered	T1,T2,T10

 LINE       12179
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T31,T25,T28
1	1	1	Covered	T1,T2,T10

 LINE       12194
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T17
1	1	1	Covered	T1,T2,T10

 LINE       12209
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T17,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12224
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T17
1	1	1	Covered	T1,T2,T10

 LINE       12239
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T23,T25
1	1	1	Covered	T1,T2,T10

 LINE       12254
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T23,T25
1	1	1	Covered	T1,T2,T10

 LINE       12269
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T23,T30
1	1	1	Covered	T1,T2,T10

 LINE       12284
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12289
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T23,T24
1	1	1	Covered	T1,T2,T10

 LINE       12294
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T23,T25
1	1	1	Covered	T1,T2,T10

 LINE       12299
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12304
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12309
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T30,T46
1	1	1	Covered	T1,T2,T7

 LINE       12314
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T17,T23
1	1	1	Covered	T1,T2,T10

 LINE       12319
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T24
1	1	1	Covered	T1,T2,T10

 LINE       12324
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T23
1	1	1	Covered	T1,T2,T10

 LINE       12337
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T23
1	1	1	Covered	T10,T13,T4

 LINE       12340
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T25,T28,T45
1	1	1	Covered	T10,T13,T4

 LINE       12343
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T24,T28
1	1	1	Covered	T10,T13,T4

 LINE       12346
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T5,T17
1	1	1	Covered	T10,T13,T4

 LINE       12349
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T25,T30
1	1	1	Covered	T10,T13,T4

 LINE       12352
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12355
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T24,T28
1	1	1	Covered	T10,T13,T4

 LINE       12358
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T24,T25,T28
1	1	1	Covered	T10,T13,T4

 LINE       12361
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T25,T30
1	1	1	Covered	T10,T13,T4

 LINE       12364
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T25
1	1	1	Covered	T10,T13,T4

 LINE       12367
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T25,T28
1	1	1	Covered	T1,T2,T10

 LINE       12382
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T23,T24
1	1	1	Covered	T1,T2,T10

 LINE       12397
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T25,T30,T45
1	1	1	Covered	T1,T2,T10

 LINE       12412
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T25,T30
1	1	1	Covered	T1,T2,T10

 LINE       12427
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T24,T28
1	1	1	Covered	T1,T2,T10

 LINE       12442
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T17,T23,T25
1	1	1	Covered	T1,T2,T10

 LINE       12457
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12472
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12487
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T24,T25
1	1	1	Covered	T1,T2,T10

 LINE       12502
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T25
1	1	1	Covered	T1,T2,T10

 LINE       12517
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T23,T25
1	1	1	Covered	T10,T13,T4

 LINE       12520
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T25
1	1	1	Covered	T1,T2,T10

 LINE       12535
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12538
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T23,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12541
 EXPRESSION (addr_hit[61] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T31,T23,T25
1	1	1	Covered	T1,T2,T10

 LINE       12556
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T28
1	1	1	Covered	T1,T2,T10

 LINE       12571
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T17,T24
1	1	1	Covered	T10,T13,T4

 LINE       12574
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12577
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T25,T28
1	1	1	Covered	T10,T13,T4

 LINE       12580
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T17,T24
1	1	1	Covered	T10,T13,T4

 LINE       12583
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T17,T23
1	1	1	Covered	T10,T13,T4

 LINE       12586
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12589
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T23
1	1	1	Covered	T10,T13,T4

 LINE       12592
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T23,T51
1	1	1	Covered	T10,T13,T4

 LINE       12595
 EXPRESSION (addr_hit[71] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T23
1	1	1	Covered	T10,T13,T4

 LINE       12598
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T25,T28,T47
1	1	1	Covered	T10,T13,T4

 LINE       12601
 EXPRESSION (addr_hit[73] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T17,T23
1	1	1	Covered	T1,T2,T10

 LINE       12616
 EXPRESSION (addr_hit[74] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T25,T28
1	1	1	Covered	T1,T2,T10

 LINE       12631
 EXPRESSION (addr_hit[75] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T25,T30
1	1	1	Covered	T1,T2,T10

 LINE       12646
 EXPRESSION (addr_hit[76] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T23,T24
1	1	1	Covered	T1,T2,T7

 LINE       12661
 EXPRESSION (addr_hit[77] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T24,T28
1	1	1	Covered	T1,T2,T10

 LINE       12676
 EXPRESSION (addr_hit[78] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T23,T25,T30
1	1	1	Covered	T1,T2,T10

 LINE       12691
 EXPRESSION (addr_hit[79] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T24,T30
1	1	1	Covered	T1,T2,T10

 LINE       12706
 EXPRESSION (addr_hit[80] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T23,T24
1	1	1	Covered	T1,T2,T10

 LINE       12721
 EXPRESSION (addr_hit[81] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T12,T25
1	1	1	Covered	T1,T2,T10

 LINE       12736
 EXPRESSION (addr_hit[82] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T25,T45,T46
1	1	1	Covered	T1,T2,T10

 LINE       12751
 EXPRESSION (addr_hit[83] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T17
1	1	1	Covered	T10,T13,T4

 LINE       12754
 EXPRESSION (addr_hit[84] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T17,T24
1	1	1	Covered	T1,T2,T10

 LINE       12769
 EXPRESSION (addr_hit[85] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T23,T24,T45
1	1	1	Covered	T10,T13,T4

 LINE       12772
 EXPRESSION (addr_hit[86] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T24,T30,T45
1	1	1	Covered	T10,T13,T4

 LINE       12775
 EXPRESSION (addr_hit[87] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T12,T24,T28
1	1	1	Covered	T1,T2,T10

 LINE       12790
 EXPRESSION (addr_hit[88] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T1,T2,T10
1	1	0	Covered	T2,T25,T28
1	1	1	Covered	T1,T2,T10

 LINE       12805
 EXPRESSION (addr_hit[89] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T17
1	1	1	Covered	T10,T13,T4

 LINE       12810
 EXPRESSION (addr_hit[90] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T25
1	1	1	Covered	T10,T13,T4

 LINE       12813
 EXPRESSION (addr_hit[91] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T10,T13
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T4

 LINE       12814
 EXPRESSION (addr_hit[91] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T12,T26
1	1	1	Covered	T10,T13,T4