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 LINE       12819
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T23,T24
1	1	1	Covered	T10,T13,T4

 LINE       12824
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T10,T13
1	1	0	Not Covered
1	1	1	Covered	T10,T4,T11

 LINE       12825
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12842
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T17,T23,T25
1	1	1	Covered	T10,T13,T4

 LINE       12847
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T24,T25
1	1	1	Not Covered

 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T2,T25,T51
1	1	1	Covered	T10,T13,T4

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T24,T25
1	1	1	Covered	T10,T13,T4

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T10
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T12,T25,T52
1	1	1	Covered	T10,T13,T4

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T10,T13
1	1	0	Covered	T53
1	1	1	Covered	T10,T13,T4

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3