Unified Coverage Report :: Module :: flash_ctrl_info_cfg

Module : flash_ctrl_info_cfg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg	0.00	0.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg	0.00	0.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg	0.00	0.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg	0.00	0.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg	0.00	0.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg	0.00	0.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_creator_mubi	0.00	0.00				0.00
u_owner_mubi	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_creator_mubi	0.00	0.00				0.00
u_owner_mubi	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_creator_mubi	0.00	0.00				0.00
u_owner_mubi	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_creator_mubi	0.00	0.00				0.00
u_owner_mubi	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_creator_mubi	0.00	0.00				0.00
u_owner_mubi	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_creator_mubi	0.00	0.00				0.00
u_owner_mubi	0.00	0.00				0.00

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=0,gen_info_priv[0].CurAddr=0,gen_info_priv[1].CurAddr=1,gen_info_priv[2].CurAddr=2,gen_info_priv[3].CurAddr=3,gen_info_priv[4].CurAddr=4,gen_info_priv[5].CurAddr=5,gen_info_priv[6].CurAddr=6,gen_info_priv[7].CurAddr=7,gen_info_priv[8].CurAddr=8,gen_info_priv[9].CurAddr=9 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	107	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
103	0	1
107	0	1
111	0	1
116	0	1
120	0	7

---

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=1,gen_info_priv[0].CurAddr=512,gen_info_priv[1].CurAddr=513,gen_info_priv[2].CurAddr=514,gen_info_priv[3].CurAddr=515,gen_info_priv[4].CurAddr=516,gen_info_priv[5].CurAddr=517,gen_info_priv[6].CurAddr=518,gen_info_priv[7].CurAddr=519,gen_info_priv[8].CurAddr=520,gen_info_priv[9].CurAddr=521 + Bank=1,InfoSel=1,gen_info_priv[0].CurAddr=768,gen_info_priv[1].CurAddr=769,gen_info_priv[2].CurAddr=770,gen_info_priv[3].CurAddr=771,gen_info_priv[4].CurAddr=772,gen_info_priv[5].CurAddr=773,gen_info_priv[6].CurAddr=774,gen_info_priv[7].CurAddr=775,gen_info_priv[8].CurAddr=776,gen_info_priv[9].CurAddr=777 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
99	0	8
120	0	2
127	0	1

---

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=0,InfoSel=2,gen_info_priv[0].CurAddr=1024,gen_info_priv[1].CurAddr=1025,gen_info_priv[2].CurAddr=1026,gen_info_priv[3].CurAddr=1027,gen_info_priv[4].CurAddr=1028,gen_info_priv[5].CurAddr=1029,gen_info_priv[6].CurAddr=1030,gen_info_priv[7].CurAddr=1031,gen_info_priv[8].CurAddr=1032,gen_info_priv[9].CurAddr=1033 + Bank=1,InfoSel=2,gen_info_priv[0].CurAddr=1280,gen_info_priv[1].CurAddr=1281,gen_info_priv[2].CurAddr=1282,gen_info_priv[3].CurAddr=1283,gen_info_priv[4].CurAddr=1284,gen_info_priv[5].CurAddr=1285,gen_info_priv[6].CurAddr=1286,gen_info_priv[7].CurAddr=1287,gen_info_priv[8].CurAddr=1288,gen_info_priv[9].CurAddr=1289 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
99	0	7
120	0	3
127	0	1

---

Line Coverage for Module : flash_ctrl_info_cfg ( parameter Bank=1,InfoSel=0,gen_info_priv[0].CurAddr=256,gen_info_priv[1].CurAddr=257,gen_info_priv[2].CurAddr=258,gen_info_priv[3].CurAddr=259,gen_info_priv[4].CurAddr=260,gen_info_priv[5].CurAddr=261,gen_info_priv[6].CurAddr=262,gen_info_priv[7].CurAddr=263,gen_info_priv[8].CurAddr=264,gen_info_priv[9].CurAddr=265 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
120	0	10
127	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	103	1	0	0.00
CONT_ASSIGN	107	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
103	0	1
107	0	1
111	0	1
116	0	1
120	0	7

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
99	0	8
120	0	2
127	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
99	0	7
120	0	3
127	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
120	0	10
127	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
99	0	8
120	0	2
127	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	62	1	0	0.00
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	99	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
CONT_ASSIGN	127	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_info_cfg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
62	0	1
72	0	1
99	0	7
120	0	3
127	0	1