Unified Coverage Report :: Module :: prim_edge_detector

Module : prim_edge_detector

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prog_empty_event	0.00	0.00	0.00			0.00
tb.dut.u_prog_lvl_event	0.00	0.00	0.00			0.00
tb.dut.u_rd_full_event	0.00	0.00	0.00			0.00
tb.dut.u_rd_lvl_event	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_prog_empty_event

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prog_lvl_event

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_rd_full_event

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_rd_lvl_event

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_edge_detector

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
ALWAYS	48	3	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
45	0	1
48	0	2
49	0	1
52	0	1
53	0	1

---

Cond Coverage for Module : prim_edge_detector

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_edge_detector

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	48	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_prog_empty_event

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
ALWAYS	48	3	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
45	0	1
48	0	2
49	0	1
52	0	1
53	0	1

---

Cond Coverage for Instance : tb.dut.u_prog_empty_event

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_prog_empty_event

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	48	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_prog_lvl_event

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
ALWAYS	48	3	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
45	0	1
48	0	2
49	0	1
52	0	1
53	0	1

---

Cond Coverage for Instance : tb.dut.u_prog_lvl_event

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_prog_lvl_event

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	48	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_rd_full_event

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
ALWAYS	48	3	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
45	0	1
48	0	2
49	0	1
52	0	1
53	0	1

---

Cond Coverage for Instance : tb.dut.u_rd_full_event

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_rd_full_event

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	48	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_rd_lvl_event

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
ALWAYS	48	3	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	53	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
45	0	1
48	0	2
49	0	1
52	0	1
53	0	1

---

Cond Coverage for Instance : tb.dut.u_rd_lvl_event

	Total	Covered	Percent
Conditions	6	0	0.00
Logical	6	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_rd_lvl_event

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	48	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered