Unified Coverage Report :: Module :: flash_ctrl

Module : flash_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
16.65	0.00	0.00	66.62		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	16.65	0.00	0.00	66.62		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
16.65	0.00	0.00	66.62		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
53.15	51.96	51.79	49.37	0.00	66.43	99.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
flash_ctrl_core_csr_assert	100.00						100.00
gen_alert_senders[0].u_alert_sender	70.00			70.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	70.00			70.00
gen_alert_senders[3].u_alert_sender	100.00			100.00
gen_alert_senders[4].u_alert_sender	77.78			77.78
tlul_assert_device	32.98	0.00				0.00	98.95
u_ctrl_arb	0.00	0.00	0.00		0.00	0.00
u_disable_buf	0.00	0.00
u_eflash	33.82	26.67	20.77	18.83	0.00	36.67	100.00
u_exec_en_buf	0.00	0.00
u_flash_ctrl_erase	0.00	0.00	0.00			0.00
u_flash_ctrl_prog	0.00	0.00	0.00	0.00		0.00
u_flash_ctrl_rd	0.00	0.00	0.00	0.00	0.00	0.00
u_flash_hw_if	8.45	0.00	0.00	42.26	0.00	0.00
u_flash_mp	0.00	0.00	0.00			0.00
u_intr_corr_err	0.00	0.00	0.00			0.00
u_intr_op_done	0.00	0.00	0.00			0.00
u_intr_prog_empty	0.00	0.00	0.00			0.00
u_intr_prog_lvl	0.00	0.00	0.00			0.00
u_intr_rd_full	0.00	0.00	0.00			0.00
u_intr_rd_lvl	0.00	0.00	0.00			0.00
u_lc_escalation_en_sync	0.00	0.00				0.00
u_lc_seed_hw_rd_en_sync	0.00	0.00				0.00
u_lfsr	0.00			0.00
u_prog_empty_event	0.00	0.00	0.00			0.00
u_prog_fifo	0.00	0.00	0.00			0.00
u_prog_lvl_event	0.00	0.00	0.00			0.00
u_prog_tl_gate	0.00	0.00	0.00		0.00	0.00
u_rd_full_event	0.00	0.00	0.00			0.00
u_rd_lvl_event	0.00	0.00	0.00			0.00
u_reg_core	91.77	98.63	97.12	65.77		97.32	100.00
u_reg_idle	0.00	0.00				0.00
u_region_cfg	0.00	0.00				0.00
u_sw_rd_fifo	0.00	0.00	0.00			0.00
u_tl_adapter_eflash	25.00	0.00	0.00	100.00		0.00
u_tl_gate	0.00	0.00	0.00		0.00	0.00
u_to_prog_fifo	0.00	0.00	0.00			0.00
u_to_rd_fifo	0.00	0.00	0.00	0.00		0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl

	Line No.	Total	Covered	Percent
TOTAL		140	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	416	1	0	0.00
CONT_ASSIGN	417	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	420	1	0	0.00
CONT_ASSIGN	421	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	423	1	0	0.00
CONT_ASSIGN	424	1	0	0.00
CONT_ASSIGN	425	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
CONT_ASSIGN	511	1	0	0.00
CONT_ASSIGN	576	1	0	0.00
CONT_ASSIGN	580	1	0	0.00
CONT_ASSIGN	582	1	0	0.00
CONT_ASSIGN	626	1	0	0.00
CONT_ASSIGN	631	1	0	0.00
ALWAYS	635	5	0	0.00
CONT_ASSIGN	673	1	0	0.00
CONT_ASSIGN	674	1	0	0.00
CONT_ASSIGN	675	1	0	0.00
CONT_ASSIGN	695	1	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	730	1	0	0.00
ALWAYS	751	7	0	0.00
CONT_ASSIGN	784	1	0	0.00
CONT_ASSIGN	785	1	0	0.00
CONT_ASSIGN	856	1	0	0.00
CONT_ASSIGN	858	1	0	0.00
CONT_ASSIGN	859	1	0	0.00
CONT_ASSIGN	860	1	0	0.00
CONT_ASSIGN	861	1	0	0.00
CONT_ASSIGN	862	1	0	0.00
CONT_ASSIGN	863	1	0	0.00
CONT_ASSIGN	864	1	0	0.00
CONT_ASSIGN	865	1	0	0.00
CONT_ASSIGN	866	1	0	0.00
CONT_ASSIGN	867	1	0	0.00
CONT_ASSIGN	869	1	0	0.00
CONT_ASSIGN	872	1	0	0.00
CONT_ASSIGN	875	1	0	0.00
CONT_ASSIGN	878	1	0	0.00
CONT_ASSIGN	880	1	0	0.00
CONT_ASSIGN	882	1	0	0.00
CONT_ASSIGN	886	1	0	0.00
CONT_ASSIGN	887	1	0	0.00
CONT_ASSIGN	888	1	0	0.00
CONT_ASSIGN	889	1	0	0.00
CONT_ASSIGN	890	1	0	0.00
CONT_ASSIGN	891	1	0	0.00
CONT_ASSIGN	892	1	0	0.00
CONT_ASSIGN	893	1	0	0.00
CONT_ASSIGN	894	1	0	0.00
CONT_ASSIGN	895	1	0	0.00
CONT_ASSIGN	896	1	0	0.00
CONT_ASSIGN	897	1	0	0.00
CONT_ASSIGN	898	1	0	0.00
CONT_ASSIGN	899	1	0	0.00
CONT_ASSIGN	900	1	0	0.00
CONT_ASSIGN	901	1	0	0.00
CONT_ASSIGN	903	1	0	0.00
CONT_ASSIGN	904	1	0	0.00
CONT_ASSIGN	905	1	0	0.00
CONT_ASSIGN	906	1	0	0.00
CONT_ASSIGN	907	1	0	0.00
CONT_ASSIGN	913	1	0	0.00
CONT_ASSIGN	937	1	0	0.00
CONT_ASSIGN	942	1	0	0.00
CONT_ASSIGN	945	1	0	0.00
CONT_ASSIGN	948	1	0	0.00
CONT_ASSIGN	950	1	0	0.00
CONT_ASSIGN	958	1	0	0.00
CONT_ASSIGN	998	1	0	0.00
CONT_ASSIGN	1002	1	0	0.00
CONT_ASSIGN	1014	1	0	0.00
CONT_ASSIGN	1015	1	0	0.00
CONT_ASSIGN	1029	1	0	0.00
CONT_ASSIGN	1043	1	0	0.00
CONT_ASSIGN	1044	1	0	0.00
CONT_ASSIGN	1062	1	0	0.00
CONT_ASSIGN	1063	1	0	0.00
CONT_ASSIGN	1064	1	0	0.00
CONT_ASSIGN	1065	1	0	0.00
CONT_ASSIGN	1066	1	0	0.00
CONT_ASSIGN	1067	1	0	0.00
CONT_ASSIGN	1068	1	0	0.00
CONT_ASSIGN	1069	1	0	0.00
CONT_ASSIGN	1070	1	0	0.00
CONT_ASSIGN	1071	1	0	0.00
CONT_ASSIGN	1092	1	0	0.00
CONT_ASSIGN	1093	1	0	0.00
CONT_ASSIGN	1094	1	0	0.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1096	1	0	0.00
CONT_ASSIGN	1097	1	0	0.00
CONT_ASSIGN	1098	1	0	0.00
CONT_ASSIGN	1099	1	0	0.00
CONT_ASSIGN	1100	1	0	0.00
CONT_ASSIGN	1101	1	0	0.00
CONT_ASSIGN	1102	1	0	0.00
CONT_ASSIGN	1103	1	0	0.00
CONT_ASSIGN	1115	1	0	0.00
CONT_ASSIGN	1117	1	0	0.00
CONT_ASSIGN	1118	1	0	0.00
CONT_ASSIGN	1119	1	0	0.00
CONT_ASSIGN	1120	1	0	0.00
CONT_ASSIGN	1121	1	0	0.00
CONT_ASSIGN	1122	1	0	0.00
CONT_ASSIGN	1123	1	0	0.00
CONT_ASSIGN	1124	1	0	0.00
CONT_ASSIGN	1128	1	0	0.00
CONT_ASSIGN	1128	1	0	0.00
CONT_ASSIGN	1129	1	0	0.00
CONT_ASSIGN	1129	1	0	0.00
CONT_ASSIGN	1133	1	0	0.00
CONT_ASSIGN	1133	1	0	0.00
CONT_ASSIGN	1134	1	0	0.00
CONT_ASSIGN	1134	1	0	0.00
ALWAYS	1140	5	0	0.00
CONT_ASSIGN	1256	1	0	0.00
CONT_ASSIGN	1257	1	0	0.00
CONT_ASSIGN	1290	1	0	0.00
CONT_ASSIGN	1291	1	0	0.00
CONT_ASSIGN	1307	1	0	0.00
CONT_ASSIGN	1418	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
415	0	1
416	0	1
417	0	1
418	0	1
419	0	1
420	0	1
421	0	1
422	0	1
423	0	1
424	0	1
425	0	1
426	0	1
511	0	1
576	0	1
580	0	1
582	0	1
626	0	1
631	0	1
635	0	1
636	0	1
637	0	1
639	0	1
640	0	1
673	0	1
674	0	1
675	0	1
695	0	1
699	0	1
730	0	1
751	0	1
753	0	1
754	0	1
757	0	1
758	0	1
761	0	1
762	0	1
784	0	1
785	0	1
856	0	1
858	0	1
859	0	1
860	0	1
861	0	1
862	0	1
863	0	1
864	0	1
865	0	1
866	0	1
867	0	1
869	0	1
872	0	1
875	0	1
878	0	1
880	0	1
882	0	1
886	0	1
887	0	1
888	0	1
889	0	1
890	0	1
891	0	1
892	0	1
893	0	1
894	0	1
895	0	1
896	0	1
897	0	1
898	0	1
899	0	1
900	0	1
901	0	1
903	0	1
904	0	1
905	0	1
906	0	1
907	0	1
913	0	1
937	0	1
942	0	1
945	0	1
948	0	1
950	0	1
958	0	1
998	0	1
1002	0	1
1014	0	1
1015	0	1
1029	0	1
1043	0	1
1044	0	1
1062	0	1
1063	0	1
1064	0	1
1065	0	1
1066	0	1
1067	0	1
1068	0	1
1069	0	1
1070	0	1
1071	0	1
1092	0	1
1093	0	1
1094	0	1
1095	0	1
1096	0	1
1097	0	1
1098	0	1
1099	0	1
1100	0	1
1101	0	1
1102	0	1
1103	0	1
1115	0	1
1117	0	1
1118	0	1
1119	0	1
1120	0	1
1121	0	1
1122	0	1
1123	0	1
1124	0	1
1128	0	2
1129	0	2
1133	0	2
1134	0	2
1140	0	1
1141	0	1
1142	0	1
1144	0	1
1145	0	1
1256	0	1
1257	0	1
1290	0	1
1291	0	1
1307	0	1
1418	0	1

---

Cond Coverage for Module : flash_ctrl

	Total	Covered	Percent
Conditions	141	0	0.00
Logical	141	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       341
 EXPRESSION (sw_wvalid & prog_op_valid)
             ----1----   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       423
 EXPRESSION (op_type == FlashOpRead)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       424
 EXPRESSION (op_type == FlashOpProgram)
            -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       425
 EXPRESSION (op_type == FlashOpErase)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       426
 EXPRESSION (if_sel == SwSel)
            --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       433
 EXPRESSION (((~sw_sel)) & rd_ctrl_wen)
             -----1-----   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       511
 EXPRESSION (op_start & prog_op)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       562
 EXPRESSION (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done)
             --------1--------   ----2---   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       580
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgNormal] & reg2hw.prog_type_en.normal.q)
             -----------------------1----------------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       582
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgRepair] & reg2hw.prog_type_en.repair.q)
             -----------------------1----------------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       626
 EXPRESSION (reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead))
             -----------1----------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       626
 SUB-EXPRESSION (reg2hw.control.op.q == FlashOpRead)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       639
 EXPRESSION (adapter_req & sw_rfifo_rvalid)
             -----1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       652
 EXPRESSION (sw_rfifo_rvalid | rd_no_op_d)
             -------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       652
 EXPRESSION (adapter_rvalid | rd_no_op_q)
             -------1------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       673
 EXPRESSION (sw_sel & rd_ctrl_wen)
             ---1--   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       699
 EXPRESSION (op_start & rd_op)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       700
 EXPRESSION (sw_sel ? sw_rfifo_wready : lcmgr_rready)
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       730
 EXPRESSION (op_start & erase_op)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       794
 EXPRESSION (rd_flash_ovfl | prog_flash_ovfl)
             ------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashErasePage))
             ----1---   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashErasePage)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashEraseBank))
             ----1---   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashEraseBank)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       867
 EXPRESSION (flash_phy_busy | ctrl_init_busy)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       869
 EXPRESSION (ctrl_initialized & ((~flash_phy_busy)))
             --------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       875
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       913
 SUB-EXPRESSION (flash_phy_req.req & (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase))
                 --------1--------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       913
 SUB-EXPRESSION (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase)
                 ---------1--------   -----------2----------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       937
 EXPRESSION ((sw_ctrl_done & ((|sw_ctrl_err))) | flash_phy_rsp.macro_err | update_err)
             ----------------1----------------   -----------2-----------   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       937
 SUB-EXPRESSION (sw_ctrl_done & ((|sw_ctrl_err)))
                 ------1-----   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe)
                 --------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe)
                 ----------------1----------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe)
                 --------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1071
 EXPRESSION (sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | sw_ctrl_err.prog_err)
             ---------1--------   ---------2--------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       1115
 EXPRESSION (intg_err | eflash_cmd_intg_err | tl_gate_intg_err | tl_prog_gate_intg_err)
             ----1---   ---------2---------   --------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       1123
 EXPRESSION (rd_cnt_err | prog_cnt_err)
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1124
 EXPRESSION (flash_phy_rsp.fifo_err | adapter_fifo_err)
             -----------1----------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       1129
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1129
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1144
 EXPRESSION (sw_rfifo_wen & sw_rfifo_wready)
             ------1-----   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1145
 EXPRESSION (prog_fifo_rvalid & prog_fifo_ren)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1182
 EXPRESSION (prog_fifo_rd_q & (reg2hw.fifo_lvl.prog.q == 5'(prog_fifo_depth)))
             -------1------   -----------------------2-----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1182
 SUB-EXPRESSION (reg2hw.fifo_lvl.prog.q == 5'(prog_fifo_depth))
                -----------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1234
 EXPRESSION (sw_rd_fifo_wr_q & (reg2hw.fifo_lvl.rd.q == sw_rfifo_depth))
             -------1-------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1234
 SUB-EXPRESSION (reg2hw.fifo_lvl.rd.q == sw_rfifo_depth)
                --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1418
 EXPRESSION (prog_op_valid | rd_op_valid | erase_op_valid)
             ------1------   -----2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : flash_ctrl

	Total	Covered	Percent
Totals	122	102	83.61
Total Bits	2750	1832	66.62
Total Bits 0->1	1375	1050	76.36
Total Bits 1->0	1375	782	56.87

Ports	122	102	83.61
Port Bits	2750	1832	66.62
Port Bits 0->1	1375	1050	76.36
Port Bits 1->0	1375	782	56.87

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T1,T2,T7	INPUT
lc_owner_seed_sw_rw_en_i[3:0]	Yes	Yes	T1,T7,T9	Yes	T1,T2,T7	INPUT
lc_iso_part_sw_rd_en_i[3:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
lc_iso_part_sw_wr_en_i[3:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
lc_seed_hw_rd_en_i[3:0]	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
lc_nvm_debug_en_i[3:0]	No	No		No		INPUT
core_tl_i.d_ready	Yes	Yes	T10,T4,T11	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T10	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T4	Yes	T2,T10,T4	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T10	Yes	T2,T10,T7	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T2,T10,T7	Yes	T2,T3,T10	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
core_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
core_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T4,T12	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T10	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T10	Yes	T1,T2,T10	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T10,T4,T11	Yes	T1,T2,T3	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T11	Yes	T2,T3,T4	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T2,T4,T11	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T8	Yes	T2,T4,T11	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T13	Yes	T2,T8,T4	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T2,T4,T11	Yes	T1,T2,T13	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T2,T11,T12	Yes	T2,T3,T8	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T11	Yes	T2,T11,T12	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T2,T8,T4	Yes	T2,T4,T11	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T2,T4,T11	Yes	T1,T2,T4	INPUT
prim_tl_i.a_valid	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	INPUT
prim_tl_o.a_ready	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
prim_tl_o.d_error	Yes	Yes	T5,T6,T14	Yes	T2,T12,T5	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T5,T15	Yes	T11,T5,T15	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T11,*T12	Yes	T2,T11,T12	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T11,T5,T15	Yes	T2,T11,T12	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T2,*T11,*T12	Yes	T2,T11,T12	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T2,T11,T12	Yes	T2,T11,T12	OUTPUT
mem_tl_i.d_ready	Yes	Yes	T10,T4,T11	Yes	T1,T2,T3	INPUT
mem_tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T7,T12	Yes	T2,T12,T5	INPUT
mem_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T12,T5	Yes	T2,T7,T9	INPUT
mem_tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T4,T16	INPUT
mem_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_data[31:0]	Yes	Yes	T2,T3,T7	Yes	T2,T9,T12	INPUT
mem_tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T9	Yes	T2,T7,T4	INPUT
mem_tl_i.a_address[31:0]	Yes	Yes	T2,T12,T5	Yes	T2,T3,T7	INPUT
mem_tl_i.a_source[7:0]	Yes	Yes	T2,T4,T12	Yes	T2,T7,T12	INPUT
mem_tl_i.a_size[1:0]	Yes	Yes	T2,T3,T9	Yes	T2,T4,T12	INPUT
mem_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_i.a_opcode[2:0]	Yes	Yes	T2,T12,T5	Yes	T2,T3,T12	INPUT
mem_tl_i.a_valid	Yes	Yes	T2,T12,T5	Yes	T2,T12,T5	INPUT
mem_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T4,T12	OUTPUT
mem_tl_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
mem_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T2,*T4,*T12	Yes	T1,T2,T3	OUTPUT
mem_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_data[31:0]	Yes	Yes	T2,T12,T17	Yes	T2,T12,T17	OUTPUT
mem_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_source[7:0]	Yes	Yes	T2,T12,T5	Yes	T2,T12,T5	OUTPUT
mem_tl_o.d_size[1:0]	Yes	Yes	T2,T12,T5	Yes	T2,T12,T5	OUTPUT
mem_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_opcode[0]	Yes	Yes	*T2,*T12,*T5	Yes	T2,T12,T5	OUTPUT
mem_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_o.d_valid	Yes	Yes	T2,T12,T5	Yes	T2,T12,T5	OUTPUT
otp_o.addr_req	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
otp_o.data_req	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
otp_i.seed_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
otp_i.rand_key[127:0]	Yes	Yes	T9,T18,T19	Yes	T1,T2,T9	INPUT
otp_i.key[127:0]	Yes	Yes	T7,T8,T20	Yes	T1,T7,T8	INPUT
otp_i.addr_ack	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
otp_i.data_ack	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
rma_req_i[3:0]	No	No		No		INPUT
rma_seed_i[31:0]	No	No		No		INPUT
rma_ack_o[3:0]	No	No		No		OUTPUT
pwrmgr_o.flash_idle	No	No		No		OUTPUT
keymgr_o.seeds[0][3]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][9:7]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][11]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][17:15]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][21:19]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][23]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][26]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][32:29]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][35:34]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][40:39]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][49]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][52:51]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][55]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][57]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][60:59]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][63]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][65]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][67]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][69]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][71]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][73]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][77:76]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][81]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][84]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][90:87]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][98:93]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][101:100]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][103]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][106]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][115:110]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][118]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][120]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][123:122]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][129:126]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][131]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][138:134]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][142:141]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][147:144]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][150:149]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][154:153]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][162]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][164]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][171:168]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][174]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][176]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][178]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][181:180]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][186:183]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][190:189]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][192]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][195]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][200:199]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][202]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][207:206]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][211:209]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][216:214]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][218]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][221]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][224:223]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][228:226]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][235]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][240:239]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][245]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][249:248]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[0][254:253]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][3:1]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][6:5]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][13:8]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][19:15]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][21]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][24]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][28:27]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][30]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][34:33]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][36]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][44:38]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][52]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][57:56]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][61:60]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][65]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][67]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][70]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][73]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][76]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][81]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][83]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][87:85]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][91:90]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][93]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][95]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][100]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][103]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][106:105]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][110:108]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][114:112]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][120:117]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][124:122]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][129:127]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][132]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][136:134]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][138]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][142:140]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][148:146]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][152:150]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][155]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][158]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][160]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][169:164]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][172:171]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][175:174]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][177]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][181:180]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][183]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][185]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][188]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][190]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][192]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][202:197]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][205:204]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][208:207]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][214:213]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][217]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][225:220]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][229:228]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][231]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][238:235]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][242:240]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][244]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][247:246]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][249]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][251]	No	No		Yes	T1,T2,T7	OUTPUT
keymgr_o.seeds[1][255:254]	No	No		Yes	T1,T2,T7	OUTPUT
Other bits of keymgr_o.seeds[1:0][255:0]	No	No		No		OUTPUT
cio_tck_i	No	No		No		INPUT
cio_tms_i	No	No		No		INPUT
cio_tdi_i	No	No		No		INPUT
cio_tdo_en_o	No	No		No		OUTPUT
cio_tdo_o	No	No		No		OUTPUT
intr_corr_err_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
intr_prog_empty_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
intr_prog_lvl_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
intr_rd_full_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
intr_rd_lvl_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
intr_op_done_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T10,T13,T4	Yes	T10,T13,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T10,T4,T11	Yes	T10,T4,T11	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T10,T4,T5	Yes	T10,T4,T5	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T10,T4,T5	Yes	T10,T4,T5	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T10,T13,T4	Yes	T10,T13,T4	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T10,T13,T4	Yes	T10,T13,T4	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T10,T4,T11	Yes	T10,T4,T11	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T10,T4,T5	Yes	T10,T4,T5	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T10,T4,T5	Yes	T10,T4,T5	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T10,T13,T4	Yes	T10,T13,T4	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
fla_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	INPUT
flash_power_ready_h_i	No	No		No		INPUT
flash_test_mode_a_io[1:0]	No	No		No		INOUT
flash_test_voltage_h_io	No	No		No		INOUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : flash_ctrl

	Line No.	Total	Covered	Percent
Branches		16	0	0.00
TERNARY	875	2	0	0.00
TERNARY	1129	2	0	0.00
TERNARY	1129	2	0	0.00
TERNARY	700	2	0	0.00
IF	635	2	0	0.00
CASE	751	4	0	0.00
IF	1140	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv' or '../src/lowrisc_systems_flash_ctrl_0.1/rtl/autogen/flash_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	875	(sw_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1129	((®2hw.ecc_single_err_cnt[0].q)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1129	((®2hw.ecc_single_err_cnt[1].q)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	700	(sw_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	635	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	751	case (op_type)

Branches:

-1-	Status	Tests
FlashOpRead	Not Covered
FlashOpProgram	Not Covered
FlashOpErase	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	1140	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered