Unified Coverage Report :: Module :: prim_gf_mult

Module : prim_gf_mult

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult	0.00	0.00	0.00			0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_gf_mult

	Line No.	Total	Covered	Percent
TOTAL		30	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	83	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	97	0	0
ALWAYS	101	5	0	0.00
ALWAYS	111	7	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
ROUTINE	137	2	0	0.00
ROUTINE	148	5	0	0.00
ROUTINE	163	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	0	1
83	0	1
85	0	1
97		unreachable
101	0	1
102	0	1
103	0	1
104		unreachable
105	0	1
106	0	1
			==> MISSING_ELSE
111	0	1
112	0	1
113	0	1
114	0	1
115		unreachable
116		unreachable
117	0	1
118	0	1
119	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
129	0	1
137	0	1
138	0	1
148	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
164	0	1
165	0	1
166	0	1
168	0	1

---

Cond Coverage for Module : prim_gf_mult

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : prim_gf_mult

	Line No.	Total	Covered	Percent
Branches		15	0	0.00
TERNARY	125	2	0	0.00
TERNARY	129	1	0	0.00
IF	101	3	0	0.00
IF	111	3	0	0.00
TERNARY	137	2	0	0.00
TERNARY	148	2	0	0.00
TERNARY	165	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(first) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	129	(ack_o) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Not Covered

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((req_i && ack_o))
-3-:	105	if ((req_i && (int'(cnt) < (Loops - 1))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	114	if (ack_o)
-3-:	117	if (req_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	137	(operand[(Width - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	148	(init) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	165	(operand[i]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
TOTAL		30	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	83	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	97	0	0
ALWAYS	101	5	0	0.00
ALWAYS	111	7	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
ROUTINE	137	2	0	0.00
ROUTINE	148	5	0	0.00
ROUTINE	163	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	0	1
83	0	1
85	0	1
97		unreachable
101	0	1
102	0	1
103	0	1
104		unreachable
105	0	1
106	0	1
			==> MISSING_ELSE
111	0	1
112	0	1
113	0	1
114	0	1
115		unreachable
116		unreachable
117	0	1
118	0	1
119	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
129	0	1
137	0	1
138	0	1
148	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
164	0	1
165	0	1
166	0	1
168	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
Branches		15	0	0.00
TERNARY	125	2	0	0.00
TERNARY	129	1	0	0.00
IF	101	3	0	0.00
IF	111	3	0	0.00
TERNARY	137	2	0	0.00
TERNARY	148	2	0	0.00
TERNARY	165	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(first) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	129	(ack_o) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Not Covered

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((req_i && ack_o))
-3-:	105	if ((req_i && (int'(cnt) < (Loops - 1))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	114	if (ack_o)
-3-:	117	if (req_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	137	(operand[(Width - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	148	(init) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	165	(operand[i]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
TOTAL		30	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	83	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	97	0	0
ALWAYS	101	5	0	0.00
ALWAYS	111	7	0	0.00
CONT_ASSIGN	125	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
CONT_ASSIGN	129	1	0	0.00
ROUTINE	137	2	0	0.00
ROUTINE	148	5	0	0.00
ROUTINE	163	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
82	0	1
83	0	1
85	0	1
97		unreachable
101	0	1
102	0	1
103	0	1
104		unreachable
105	0	1
106	0	1
			==> MISSING_ELSE
111	0	1
112	0	1
113	0	1
114	0	1
115		unreachable
116		unreachable
117	0	1
118	0	1
119	0	1
			==> MISSING_ELSE
125	0	1
126	0	1
129	0	1
137	0	1
138	0	1
148	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
164	0	1
165	0	1
166	0	1
168	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Total	Covered	Percent
Conditions	15	0	0.00
Logical	15	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       85
 EXPRESSION (cnt == 1'b0)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       97
 EXPRESSION (int'(cnt) == (Loops - 1))
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       103
 EXPRESSION (req_i && ack_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       105
 EXPRESSION (req_i && (int'(cnt) < (Loops - 1)))
             --1--    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       125
 EXPRESSION (first ? prim_gf_mult.gen_matrix(operand_a_i, 1'b1) : prim_gf_mult.gen_matrix(vector, 1'b0))
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       129
 EXPRESSION (ack_o ? prod_d : operand_a_i)
             --1--

-1-	Status	Tests
0	Not Covered
1	Unreachable

 LINE       137
 EXPRESSION (operand[(Width - 1)] ? (((operand << 1) ^ IPoly)) : ((operand << 1)))
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 EXPRESSION (init ? seed : gf_mult2(seed))
             --1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       165
 EXPRESSION (operand[i] ? matrix_[i] : '0)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_gf_mult.u_mult

	Line No.	Total	Covered	Percent
Branches		15	0	0.00
TERNARY	125	2	0	0.00
TERNARY	129	1	0	0.00
IF	101	3	0	0.00
IF	111	3	0	0.00
TERNARY	137	2	0	0.00
TERNARY	148	2	0	0.00
TERNARY	165	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv' or '../src/lowrisc_prim_gf_mult_0/rtl/prim_gf_mult.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(first) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	129	(ack_o) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Not Covered

	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((req_i && ack_o))
-3-:	105	if ((req_i && (int'(cnt) < (Loops - 1))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	114	if (ack_o)
-3-:	117	if (req_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	137	(operand[(Width - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	148	(init) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	165	(operand[i]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered