Unified Coverage Report :: Module :: prim_intr_hw

Module : prim_intr_hw

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_intr_prog_empty	0.00	0.00	0.00			0.00
tb.dut.u_intr_prog_lvl	0.00	0.00	0.00			0.00
tb.dut.u_intr_rd_full	0.00	0.00	0.00			0.00
tb.dut.u_intr_rd_lvl	0.00	0.00	0.00			0.00
tb.dut.u_intr_op_done	0.00	0.00	0.00			0.00
tb.dut.u_intr_corr_err	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_intr_prog_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_prog_lvl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rd_full

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rd_lvl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_op_done

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_corr_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_intr_hw

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Module : prim_intr_hw

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_intr_hw

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_intr_prog_empty

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Instance : tb.dut.u_intr_prog_empty

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_intr_prog_empty

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_intr_prog_lvl

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Instance : tb.dut.u_intr_prog_lvl

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_intr_prog_lvl

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_intr_rd_full

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Instance : tb.dut.u_intr_rd_full

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_intr_rd_full

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_intr_rd_lvl

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Instance : tb.dut.u_intr_rd_lvl

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_intr_rd_lvl

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_intr_op_done

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Instance : tb.dut.u_intr_op_done

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_intr_op_done

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_intr_corr_err

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
CONT_ASSIGN	47	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	52	1	0	0.00
CONT_ASSIGN	54	1	0	0.00
ALWAYS	80	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	0	1
49	0	1
52	0	1
54	0	1
80	0	1
81	0	1
83	0	1

---

Cond Coverage for Instance : tb.dut.u_intr_corr_err

	Total	Covered	Percent
Conditions	12	0	0.00
Logical	12	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_intr_corr_err

	Line No.	Total	Covered	Percent
Branches		2	0	0.00
IF	80	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered