Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2326356	4976	0	0
DepthKnown_A	2326356	2246865	0	0
RvalidKnown_A	2326356	2246865	0	0
WreadyKnown_A	2326356	2246865	0	0
gen_passthru_fifo.paramCheckPass	211	211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	4976	0	0
T2	4442	208	0	0
T3	854	0	0	0
T4	5408	0	0	0
T7	1597	0	0	0
T8	1326	0	0	0
T9	1398	0	0	0
T10	7955	0	0	0
T12	0	280	0	0
T13	3527	0	0	0
T16	1672	0	0	0
T17	0	123	0	0
T23	0	210	0	0
T24	0	206	0	0
T25	0	220	0	0
T26	0	22	0	0
T27	0	1	0	0
T28	0	349	0	0
T29	1275	0	0	0
T30	0	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	211	211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2326356	4164	0	0
DepthKnown_A	2326356	2246865	0	0
RvalidKnown_A	2326356	2246865	0	0
WreadyKnown_A	2326356	2246865	0	0
gen_passthru_fifo.paramCheckPass	211	211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	4164	0	0
T2	4442	176	0	0
T3	854	0	0	0
T4	5408	0	0	0
T7	1597	0	0	0
T8	1326	0	0	0
T9	1398	0	0	0
T10	7955	0	0	0
T12	0	229	0	0
T13	3527	0	0	0
T16	1672	0	0	0
T17	0	107	0	0
T23	0	172	0	0
T24	0	187	0	0
T25	0	204	0	0
T26	0	22	0	0
T27	0	1	0	0
T28	0	274	0	0
T29	1275	0	0	0
T30	0	68	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	211	211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2326356	588268	0	0
DepthKnown_A	2326356	2246865	0	0
RvalidKnown_A	2326356	2246865	0	0
WreadyKnown_A	2326356	2246865	0	0
gen_passthru_fifo.paramCheckPass	211	211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	588268	0	0
T1	1675	103	0	0
T2	4442	1188	0	0
T3	854	57	0	0
T4	5408	4429	0	0
T7	1597	142	0	0
T8	1326	198	0	0
T9	1398	142	0	0
T10	7955	1280	0	0
T13	3527	2230	0	0
T16	1672	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	211	211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2326356	638873	0	0
DepthKnown_A	2326356	2246865	0	0
RvalidKnown_A	2326356	2246865	0	0
WreadyKnown_A	2326356	2246865	0	0
gen_passthru_fifo.paramCheckPass	211	211	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	638873	0	0
T1	1675	103	0	0
T2	4442	788	0	0
T3	854	57	0	0
T4	5408	2378	0	0
T7	1597	142	0	0
T8	1326	198	0	0
T9	1398	142	0	0
T10	7955	1192	0	0
T13	3527	1197	0	0
T16	1672	142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2246865	0	0
T1	1675	1609	0	0
T2	4442	4343	0	0
T3	854	800	0	0
T4	5408	5227	0	0
T7	1597	1514	0	0
T8	1326	1272	0	0
T9	1398	1319	0	0
T10	7955	7896	0	0
T13	3527	3441	0	0
T16	1672	1609	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	211	211	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0