Unified Coverage Report :: Module :: flash_ctrl_lcmgr

Module : flash_ctrl_lcmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_hw_if	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_flash_hw_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
8.45	0.00	0.00	42.26	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_cnt	0.00			0.00
u_addr_sync_reqack	0.00	0.00	0.00			0.00
u_bus_intg	0.00	0.00
u_data_intg_chk	44.38	0.00		88.75
u_data_sync_reqack	0.00	0.00	0.00			0.00
u_page_cnt	0.00			0.00
u_prim_flop_err_sts	0.00	0.00				0.00
u_rma_state_regs	0.00	0.00				0.00
u_seed_cnt	0.00			0.00
u_state_regs	0.00	0.00				0.00
u_sync_flash_init	0.00	0.00				0.00
u_sync_rma_req	0.00	0.00				0.00
u_wipe_idx_cnt	0.00			0.00
u_word_cnt	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
TOTAL		242	0	0.00
CONT_ASSIGN	149	1	0	0.00
ALWAYS	152	3	0	0.00
CONT_ASSIGN	170	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
ALWAYS	174	7	0	0.00
CONT_ASSIGN	185	1	0	0.00
ALWAYS	225	5	0	0.00
CONT_ASSIGN	241	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
ALWAYS	249	3	0	0.00
CONT_ASSIGN	259	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
ALWAYS	262	6	0	0.00
CONT_ASSIGN	276	1	0	0.00
CONT_ASSIGN	277	1	0	0.00
CONT_ASSIGN	278	1	0	0.00
ALWAYS	357	9	0	0.00
CONT_ASSIGN	378	1	0	0.00
ALWAYS	384	85	0	0.00
CONT_ASSIGN	605	1	0	0.00
ALWAYS	611	3	0	0.00
ALWAYS	668	7	0	0.00
ALWAYS	683	10	0	0.00
ALWAYS	700	2	0	0.00
CONT_ASSIGN	709	1	0	0.00
CONT_ASSIGN	710	1	0	0.00
CONT_ASSIGN	732	1	0	0.00
CONT_ASSIGN	736	1	0	0.00
CONT_ASSIGN	737	1	0	0.00
CONT_ASSIGN	749	1	0	0.00
ALWAYS	756	66	0	0.00
CONT_ASSIGN	886	1	0	0.00
CONT_ASSIGN	887	1	0	0.00
CONT_ASSIGN	888	1	0	0.00
CONT_ASSIGN	889	0	0
CONT_ASSIGN	890	0	0
CONT_ASSIGN	891	1	0	0.00
CONT_ASSIGN	892	1	0	0.00
CONT_ASSIGN	893	1	0	0.00
CONT_ASSIGN	895	1	0	0.00
CONT_ASSIGN	897	1	0	0.00
CONT_ASSIGN	900	1	0	0.00
CONT_ASSIGN	901	1	0	0.00
CONT_ASSIGN	903	1	0	0.00
CONT_ASSIGN	904	1	0	0.00
CONT_ASSIGN	906	1	0	0.00
CONT_ASSIGN	909	1	0	0.00
CONT_ASSIGN	913	1	0	0.00
CONT_ASSIGN	916	1	0	0.00
ALWAYS	927	0	0
CONT_ASSIGN	934	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
149	0	1
152	0	3
170	0	1
171	0	1
174	0	1
175	0	1
176	0	1
177	0	1
179	0	1
180	0	1
181	0	1
185	0	1
225	0	1
226	0	1
227	0	1
229	0	1
230	0	1
241	0	1
245	0	1
249	0	1
250	0	1
252	0	1
259	0	1
260	0	1
262	0	1
263	0	1
264	0	1
266	0	1
268	0	1
269	0	1
			==> MISSING_ELSE
276	0	1
277	0	1
278	0	1
357	0	1
358	0	1
359	0	1
361	0	1
362	0	1
363	0	1
			==> MISSING_ELSE
366	0	1
367	0	1
368	0	1
			==> MISSING_ELSE
378	0	1
384	0	1
387	0	1
388	0	1
389	0	1
390	0	1
393	0	1
394	0	1
395	0	1
396	0	1
397	0	1
400	0	1
402	0	1
403	0	1
404	0	1
407	0	1
409	0	1
410	0	1
413	0	1
414	0	1
417	0	1
418	0	1
421	0	1
423	0	1
425	0	1
431	0	1
432	0	1
433	0	1
434	0	1
			==> MISSING_ELSE
439	0	1
440	0	1
441	0	1
442	0	1
443	0	1
444	0	1
			==> MISSING_ELSE
449	0	1
450	0	1
451	0	1
452	0	1
453	0	1
455	0	1
			==> MISSING_ELSE
462	0	1
465	0	1
466	0	1
467	0	1
470	0	1
471	0	1
472	0	1
473	0	1
474	0	1
475	0	1
476	0	1
			==> MISSING_ELSE
481	0	1
482	0	1
483	0	1
485	0	1
486	0	1
487	0	1
489	0	1
495	0	1
496	0	1
497	0	1
			==> MISSING_ELSE
503	0	1
504	0	1
505	0	1
			==> MISSING_ELSE
510	0	1
511	0	1
512	0	1
514	0	1
518	0	1
519	0	1
520	0	1
			==> MISSING_ELSE
529	0	1
530	0	1
531	0	1
532	0	1
534	0	1
541	0	1
542	0	1
543	0	1
547	0	1
548	0	1
549	0	1
550	0	1
567	0	1
570	0	1
			==> MISSING_ELSE
605	0	1
611	0	3
668	0	1
669	0	1
670	0	1
671	0	1
673	0	1
674	0	1
675	0	1
683	0	1
684	0	1
685	0	1
686	0	1
687	0	1
688	0	1
689	0	1
			==> MISSING_ELSE
691	0	1
692	0	1
693	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
700	0	1
701	0	1
			==> MISSING_ELSE
709	0	1
710	0	1
732	0	1
736	0	1
737	0	1
749	0	1
756	0	1
757	0	1
758	0	1
759	0	1
760	0	1
761	0	1
762	0	1
763	0	1
764	0	1
765	0	1
766	0	1
767	0	1
768	0	1
769	0	1
770	0	1
772	0	1
779	0	1
780	0	1
781	0	1
782	0	1
783	0	1
			==> MISSING_ELSE
788	0	1
789	0	1
790	0	1
791	0	1
793	0	1
794	0	1
795	0	1
800	0	1
801	0	1
802	0	1
803	0	1
804	0	1
			==> MISSING_ELSE
809	0	1
810	0	1
814	0	1
815	0	1
816	0	1
817	0	1
819	0	1
820	0	1
821	0	1
826	0	1
827	0	1
828	0	1
830	0	1
831	0	1
			==> MISSING_ELSE
836	0	1
837	0	1
839	0	1
840	0	1
841	0	1
842	0	1
			==> MISSING_ELSE
847	0	1
848	0	1
849	0	1
851	0	1
852	0	1
853	0	1
854	0	1
			==> MISSING_ELSE
857	0	1
858	0	1
			==> MISSING_ELSE
863	0	1
867	0	1
868	0	1
869	0	1
886	0	1
887	0	1
888	0	1
889		unreachable
890		unreachable
891	0	1
892	0	1
893	0	1
895	0	1
897	0	1
900	0	1
901	0	1
903	0	1
904	0	1
906	0	1
909	0	1
913	0	1
916	0	1
927		unreachable
928		unreachable
			==> MISSING_ELSE
934	0	1

---

Cond Coverage for Module : flash_ctrl_lcmgr

	Total	Covered	Percent
Conditions	96	0	0.00
Logical	96	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       229
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       230
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       245
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       245
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       264
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       268
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       361
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       366
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       455
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       471
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       514
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       514
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       673
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       674
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       675
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       688
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       692
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       700
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       830
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       830
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       851
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       851
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       857
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       858
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       887
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       888
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       891
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       892
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       893
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       895
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       901
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       909
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	0	0	0	0	0	0	Not Covered
0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	1	0	Not Covered
0	0	0	0	1	0	0	Not Covered
0	0	0	1	0	0	0	Not Covered
0	0	1	0	0	0	0	Not Covered
0	1	0	0	0	0	0	Not Covered
1	0	0	0	0	0	0	Not Covered

---

FSM Coverage for Module : flash_ctrl_lcmgr

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	25	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisabled	543	Not Covered
StEntropyReseed	497	Not Covered
StIdle	430	Not Covered
StInvalid	518	Not Covered
StReadEval	476	Not Covered
StReadSeeds	455	Not Covered
StReqAddrKey	434	Not Covered
StReqDataKey	444	Not Covered
StRmaRsp	518	Not Covered
StRmaWipe	432	Not Covered
StWait	455	Not Covered

transitions	Line No.	Covered	Tests
StEntropyReseed->StDisabled	570	Not Covered
StEntropyReseed->StRmaWipe	505	Not Covered
StIdle->StDisabled	570	Not Covered
StIdle->StReqAddrKey	434	Not Covered
StIdle->StRmaWipe	432	Not Covered
StInvalid->StDisabled	570	Not Covered
StReadEval->StDisabled	570	Not Covered
StReadEval->StReadSeeds	483	Not Covered
StReadSeeds->StDisabled	570	Not Covered
StReadSeeds->StReadEval	476	Not Covered
StReadSeeds->StWait	473	Not Covered
StReqAddrKey->StDisabled	570	Not Covered
StReqAddrKey->StReqDataKey	444	Not Covered
StReqAddrKey->StRmaWipe	442	Not Covered
StReqDataKey->StDisabled	570	Not Covered
StReqDataKey->StReadSeeds	455	Not Covered
StReqDataKey->StRmaWipe	452	Not Covered
StReqDataKey->StWait	455	Not Covered
StRmaRsp->StDisabled	570	Not Covered
StRmaRsp->StInvalid	532	Not Covered
StRmaWipe->StDisabled	570	Not Covered
StRmaWipe->StInvalid	518	Not Covered
StRmaWipe->StRmaRsp	518	Not Covered
StWait->StDisabled	570	Not Covered
StWait->StEntropyReseed	497	Not Covered

Summary for FSM :: rma_state_q

	Total	Covered	Percent
States	10	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: rma_state_q

---

states	Line No.	Covered	Tests
StRmaDisabled	780	Not Covered
StRmaErase	791	Not Covered
StRmaEraseWait	804	Not Covered
StRmaIdle	795	Not Covered
StRmaInvalid	867	Not Covered
StRmaPageSel	782	Not Covered
StRmaProgram	817	Not Covered
StRmaProgramWait	831	Not Covered
StRmaRdVerify	842	Not Covered
StRmaWordSel	810	Not Covered

transitions	Line No.	Covered	Tests
StRmaErase->StRmaEraseWait	804	Not Covered
StRmaEraseWait->StRmaWordSel	810	Not Covered
StRmaIdle->StRmaDisabled	780	Not Covered
StRmaIdle->StRmaPageSel	782	Not Covered
StRmaPageSel->StRmaDisabled	789	Not Covered
StRmaPageSel->StRmaErase	791	Not Covered
StRmaPageSel->StRmaIdle	795	Not Covered
StRmaProgram->StRmaProgramWait	831	Not Covered
StRmaProgramWait->StRmaRdVerify	842	Not Covered
StRmaRdVerify->StRmaWordSel	854	Not Covered
StRmaWordSel->StRmaDisabled	815	Not Covered
StRmaWordSel->StRmaPageSel	821	Not Covered
StRmaWordSel->StRmaProgram	817	Not Covered

---

Branch Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
Branches		94	0	0.00
TERNARY	887	2	0	0.00
TERNARY	888	2	0	0.00
TERNARY	891	2	0	0.00
TERNARY	892	2	0	0.00
TERNARY	893	2	0	0.00
TERNARY	895	2	0	0.00
IF	152	2	0	0.00
IF	174	2	0	0.00
IF	225	2	0	0.00
IF	249	2	0	0.00
IF	262	4	0	0.00
IF	357	5	0	0.00
CASE	425	27	0	0.00
IF	567	2	0	0.00
IF	611	2	0	0.00
IF	668	2	0	0.00
IF	683	7	0	0.00
IF	700	2	0	0.00
CASE	772	23	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	887	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	888	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	891	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	892	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	893	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	895	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	152	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	174	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	249	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	262	if ((!rst_ni))
-2-:	264	if (((seed_phase && validate_q) && rvalid_i))
-3-:	268	if ((seed_phase && rvalid_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	357	if ((!rst_ni))
-2-:	361	if ((addr_key_req_d && addr_key_ack_q))
-3-:	366	if ((data_key_req_d && data_key_ack_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	425	case (state_q)
-2-:	431	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit]))
-3-:	433	if (init_q)
-4-:	441	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-5-:	443	if (addr_key_ack_q)
-6-:	451	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-7-:	453	if (data_key_ack_q)
-8-:	455	(provision_en_i) ? 
-9-:	471	if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds))
-10-:	474	if (done_i)
-11-:	485	if (validate_q)
-12-:	496	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait]))
-13-:	504	if (edn_ack_i)
-14-:	514	if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done))
-15-:	519	if (rma_wipe_done)
-16-:	531	if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqAddrKey	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqAddrKey	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqAddrKey	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	0	1	0	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StReadSeeds	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StReadSeeds	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Not Covered
StReadSeeds	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Not Covered
StReadEval	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StReadEval	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Not Covered
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	567	if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	611	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	668	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	683	if ((!rst_ni))
-2-:	685	if (beat_cnt_clr)
-3-:	687	if (prog_cnt_en)
-4-:	688	if ((wvalid_o && wready_i))
-5-:	691	if (rd_cnt_en)
-6-:	692	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	1	-	-	Not Covered
0	0	1	0	-	-	Not Covered
0	0	0	-	1	1	Not Covered
0	0	0	-	1	0	Not Covered
0	0	0	-	0	-	Not Covered

	LineNo.	Expression
-1-:	700	if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	772	case (rma_state_q)
-2-:	779	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	781	if (rma_wipe_req_int)
-4-:	788	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-5-:	790	if ((page_cnt < end_page))
-6-:	802	if (done_i)
-7-:	814	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-8-:	816	if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage))
-9-:	830	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i))
-10-:	839	if (done_i)
-11-:	851	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i))
-12-:	857	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StRmaIdle	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StRmaIdle	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRmaIdle	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StRmaPageSel	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StRmaPageSel	-	-	0	1	-	-	-	-	-	-	-	Not Covered
StRmaPageSel	-	-	0	0	-	-	-	-	-	-	-	Not Covered
StRmaErase	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRmaErase	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StRmaEraseWait	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRmaWordSel	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StRmaWordSel	-	-	-	-	-	0	1	-	-	-	-	Not Covered
StRmaWordSel	-	-	-	-	-	0	0	-	-	-	-	Not Covered
StRmaProgram	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StRmaProgram	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaProgramWait	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StRmaProgramWait	-	-	-	-	-	-	-	-	0	-	-	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StRmaDisabled	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRmaInvalid	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered