Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_rd
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_rd 0.00 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_flash_ctrl_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
16.65 0.00 0.00 66.62 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_bus_intg 0.00 0.00
u_cnt 0.00 0.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_rd
Line No.TotalCoveredPercent
TOTAL4400.00
ALWAYS52300.00
ALWAYS60500.00
ALWAYS96400.00
CONT_ASSIGN103100.00
CONT_ASSIGN104100.00
ALWAYS1122400.00
CONT_ASSIGN162100.00
CONT_ASSIGN163100.00
CONT_ASSIGN164100.00
CONT_ASSIGN166100.00
CONT_ASSIGN179100.00
CONT_ASSIGN181100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 0 1
53 0 1
55 0 1
60 0 1
61 0 1
62 0 1
63 0 1
65 0 1
96 0 1
97 0 1
98 0 1
99 0 1
==> MISSING_ELSE
103 0 1
104 0 1
112 0 1
113 0 1
114 0 1
115 0 1
116 0 1
118 0 1
120 0 1
122 0 1
123 0 1
124 0 1
125 0 1
==> MISSING_ELSE
132 0 1
134 0 1
135 0 1
136 0 1
138 0 1
140 0 1
141 0 1
142 0 1
144 0 1
==> MISSING_ELSE
150 0 1
152 0 1
153 0 1
154 0 1
==> MISSING_ELSE
162 0 1
163 0 1
164 0 1
166 0 1
179 0 1
181 0 1

Cond Coverage for Module : flash_ctrl_rd
TotalCoveredPercent
Conditions3300.00
Logical3300.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       71
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       98
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       103
 EXPRESSION (flash_req_o & flash_done_i)
             -----1-----   ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       125
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       132
 EXPRESSION (op_start_i & data_rdy_i)
             -----1----   -----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       144
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       152
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       166
 EXPRESSION (data_wr_o & ((|op_err_o)))
             ----1----   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       179
 EXPRESSION ((((~err_sel)) | (err_sel & op_err_o.rd_err)) ? flash_data_i : inv_data_integ)
             ----------------------1---------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       179
 SUB-EXPRESSION (((~err_sel)) | (err_sel & op_err_o.rd_err))
                 ------1-----   -------------2-------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       179
 SUB-EXPRESSION (err_sel & op_err_o.rd_err)
                 ---1---   -------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
FSM Coverage for Module : flash_ctrl_rd
Summary for FSM :: st_q
TotalCoveredPercent
States 3 0 0.00 (Not included in score)
Transitions 5 0 0.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StErr 122 Not Covered
StIdle 142 Not Covered
StNorm 125 Not Covered


transitionsLine No.CoveredTests
StErr->StIdle 153 Not Covered
StIdle->StErr 122 Not Covered
StIdle->StNorm 125 Not Covered
StNorm->StErr 144 Not Covered
StNorm->StIdle 142 Not Covered


Branch Coverage for Module : flash_ctrl_rd
Line No.TotalCoveredPercent
Branches 21 0 0.00
TERNARY 179 2 0 0.00
IF 52 2 0 0.00
IF 60 3 0 0.00
IF 96 3 0 0.00
CASE 118 11 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	179	(((~err_sel) | (err_sel & op_err_o.rd_err))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	60	if ((!rst_ni))
-2-:	62	if ((op_start_i && op_done_o))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if (((~|op_err_q) && (|op_err_d)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	118	case (st_q)
-2-:	120	if (cnt_err_o)
-3-:	123	if (op_start_i)
-4-:	125	((|op_err_d)) ? 
-5-:	134	if (txn_done)
-6-:	140	if (cnt_hit)
-7-:	144	((|op_err_d)) ? 
-8-:	152	if ((data_rdy_i && cnt_hit))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Not Covered
StIdle 0 1 1 - - - - Not Covered
StIdle 0 1 0 - - - - Not Covered
StIdle 0 0 - - - - - Not Covered
StNorm - - - 1 1 - - Not Covered
StNorm - - - 1 0 1 - Not Covered
StNorm - - - 1 0 0 - Not Covered
StNorm - - - 0 - - - Not Covered
StErr - - - - - - 1 Not Covered
StErr - - - - - - 0 Not Covered
default - - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%