Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2326356	4375	0	0
addr_rd_A	2326356	1127	0	0
bank0_info0_page_cfg_0_rd_A	2326356	1672	0	0
bank0_info0_page_cfg_1_rd_A	2326356	1797	0	0
bank0_info0_page_cfg_2_rd_A	2326356	1758	0	0
bank0_info0_page_cfg_3_rd_A	2326356	1978	0	0
bank0_info0_page_cfg_4_rd_A	2326356	1929	0	0
bank0_info0_page_cfg_5_rd_A	2326356	1966	0	0
bank0_info0_page_cfg_6_rd_A	2326356	1999	0	0
bank0_info0_page_cfg_7_rd_A	2326356	1722	0	0
bank0_info0_page_cfg_8_rd_A	2326356	1984	0	0
bank0_info0_page_cfg_9_rd_A	2326356	1880	0	0
bank0_info0_regwen_0_rd_A	2326356	1132	0	0
bank0_info0_regwen_1_rd_A	2326356	1218	0	0
bank0_info0_regwen_2_rd_A	2326356	1178	0	0
bank0_info0_regwen_3_rd_A	2326356	969	0	0
bank0_info0_regwen_4_rd_A	2326356	1216	0	0
bank0_info0_regwen_5_rd_A	2326356	899	0	0
bank0_info0_regwen_6_rd_A	2326356	1192	0	0
bank0_info0_regwen_7_rd_A	2326356	1034	0	0
bank0_info0_regwen_8_rd_A	2326356	1207	0	0
bank0_info0_regwen_9_rd_A	2326356	1013	0	0
bank0_info1_page_cfg_rd_A	2326356	1912	0	0
bank0_info1_regwen_rd_A	2326356	1198	0	0
bank0_info2_page_cfg_0_rd_A	2326356	1797	0	0
bank0_info2_page_cfg_1_rd_A	2326356	1951	0	0
bank0_info2_regwen_0_rd_A	2326356	1222	0	0
bank0_info2_regwen_1_rd_A	2326356	994	0	0
bank1_info0_page_cfg_0_rd_A	2326356	2010	0	0
bank1_info0_page_cfg_1_rd_A	2326356	1886	0	0
bank1_info0_page_cfg_2_rd_A	2326356	1712	0	0
bank1_info0_page_cfg_3_rd_A	2326356	1999	0	0
bank1_info0_page_cfg_4_rd_A	2326356	1971	0	0
bank1_info0_page_cfg_5_rd_A	2326356	1914	0	0
bank1_info0_page_cfg_6_rd_A	2326356	1859	0	0
bank1_info0_page_cfg_7_rd_A	2326356	1969	0	0
bank1_info0_page_cfg_8_rd_A	2326356	1827	0	0
bank1_info0_page_cfg_9_rd_A	2326356	1560	0	0
bank1_info0_regwen_0_rd_A	2326356	1157	0	0
bank1_info0_regwen_1_rd_A	2326356	1085	0	0
bank1_info0_regwen_2_rd_A	2326356	1136	0	0
bank1_info0_regwen_3_rd_A	2326356	1209	0	0
bank1_info0_regwen_4_rd_A	2326356	926	0	0
bank1_info0_regwen_5_rd_A	2326356	1179	0	0
bank1_info0_regwen_6_rd_A	2326356	1265	0	0
bank1_info0_regwen_7_rd_A	2326356	1113	0	0
bank1_info0_regwen_8_rd_A	2326356	957	0	0
bank1_info0_regwen_9_rd_A	2326356	1060	0	0
bank1_info1_page_cfg_rd_A	2326356	1573	0	0
bank1_info1_regwen_rd_A	2326356	892	0	0
bank1_info2_page_cfg_0_rd_A	2326356	1870	0	0
bank1_info2_page_cfg_1_rd_A	2326356	1824	0	0
bank1_info2_regwen_0_rd_A	2326356	815	0	0
bank1_info2_regwen_1_rd_A	2326356	1181	0	0
bank_cfg_regwen_rd_A	2326356	1134	0	0
default_region_rd_A	2326356	1641	0	0
exec_rd_A	2326356	1182	0	0
fifo_lvl_rd_A	2326356	1343	0	0
fifo_rst_rd_A	2326356	910	0	0
hw_info_cfg_override_rd_A	2326356	1223	0	0
intr_enable_rd_A	2326356	1958	0	0
mp_region_0_rd_A	2326356	947	0	0
mp_region_1_rd_A	2326356	1036	0	0
mp_region_2_rd_A	2326356	1161	0	0
mp_region_3_rd_A	2326356	1304	0	0
mp_region_4_rd_A	2326356	1255	0	0
mp_region_5_rd_A	2326356	1187	0	0
mp_region_6_rd_A	2326356	1276	0	0
mp_region_7_rd_A	2326356	1232	0	0
mp_region_cfg_0_rd_A	2326356	1630	0	0
mp_region_cfg_1_rd_A	2326356	1807	0	0
mp_region_cfg_2_rd_A	2326356	1622	0	0
mp_region_cfg_3_rd_A	2326356	1759	0	0
mp_region_cfg_4_rd_A	2326356	1663	0	0
mp_region_cfg_5_rd_A	2326356	1773	0	0
mp_region_cfg_6_rd_A	2326356	1868	0	0
mp_region_cfg_7_rd_A	2326356	1946	0	0
phy_alert_cfg_rd_A	2326356	328	0	0
region_cfg_regwen_0_rd_A	2326356	1168	0	0
region_cfg_regwen_1_rd_A	2326356	1203	0	0
region_cfg_regwen_2_rd_A	2326356	1065	0	0
region_cfg_regwen_3_rd_A	2326356	1177	0	0
region_cfg_regwen_4_rd_A	2326356	1198	0	0
region_cfg_regwen_5_rd_A	2326356	1071	0	0
region_cfg_regwen_6_rd_A	2326356	1126	0	0
region_cfg_regwen_7_rd_A	2326356	890	0	0
scratch_rd_A	2326356	1082	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	4375	0	0
T2	4442	171	0	0
T3	854	0	0	0
T4	5408	0	0	0
T5	0	2	0	0
T7	1597	0	0	0
T8	1326	0	0	0
T9	1398	0	0	0
T10	7955	0	0	0
T12	0	347	0	0
T13	3527	0	0	0
T16	1672	0	0	0
T17	0	50	0	0
T22	0	4	0	0
T23	0	166	0	0
T24	0	256	0	0
T25	0	218	0	0
T26	0	72	0	0
T27	0	1	0	0
T29	1275	0	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1127	0	0
T5	34388	0	0	0
T11	3146	6	0	0
T12	4866	0	0	0
T14	41168	32	0	0
T31	39985	33	0	0
T34	2886	2	0	0
T37	0	4	0	0
T38	0	296	0	0
T51	0	35	0	0
T54	0	1	0	0
T55	0	9	0	0
T56	0	39	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1672	0	0
T14	41168	141	0	0
T31	39985	67	0	0
T37	6266	16	0	0
T38	293194	284	0	0
T51	0	77	0	0
T54	3943	6	0	0
T55	0	7	0	0
T56	0	156	0	0
T61	0	10	0	0
T62	0	10	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1797	0	0
T5	34388	0	0	0
T11	3146	22	0	0
T12	4866	0	0	0
T14	41168	148	0	0
T31	39985	102	0	0
T34	2886	2	0	0
T37	0	21	0	0
T38	0	274	0	0
T51	0	109	0	0
T54	0	8	0	0
T55	0	12	0	0
T56	0	152	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1758	0	0
T14	41168	186	0	0
T31	39985	58	0	0
T37	6266	17	0	0
T38	293194	277	0	0
T51	0	119	0	0
T54	3943	2	0	0
T55	0	15	0	0
T56	0	107	0	0
T61	0	27	0	0
T62	0	5	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1978	0	0
T5	34388	0	0	0
T11	3146	11	0	0
T12	4866	0	0	0
T14	41168	162	0	0
T31	39985	59	0	0
T37	6266	21	0	0
T38	0	312	0	0
T51	0	90	0	0
T54	0	15	0	0
T55	0	36	0	0
T56	0	142	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	45	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1929	0	0
T5	34388	0	0	0
T11	3146	8	0	0
T12	4866	0	0	0
T14	41168	186	0	0
T31	39985	75	0	0
T34	2886	3	0	0
T37	0	2	0	0
T38	0	307	0	0
T51	0	92	0	0
T54	0	11	0	0
T55	0	15	0	0
T56	0	165	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1966	0	0
T14	41168	152	0	0
T31	39985	78	0	0
T37	6266	1	0	0
T38	293194	306	0	0
T51	0	95	0	0
T54	3943	5	0	0
T55	0	29	0	0
T56	0	167	0	0
T61	0	41	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	281	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1999	0	0
T5	34388	0	0	0
T11	3146	13	0	0
T12	4866	0	0	0
T14	41168	247	0	0
T31	39985	76	0	0
T34	2886	9	0	0
T37	0	35	0	0
T38	0	269	0	0
T51	0	104	0	0
T54	0	3	0	0
T55	0	15	0	0
T56	0	190	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1722	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	136	0	0
T31	39985	86	0	0
T37	6266	4	0	0
T38	0	299	0	0
T51	0	77	0	0
T54	0	6	0	0
T55	0	19	0	0
T56	0	182	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	56	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1984	0	0
T5	34388	0	0	0
T11	3146	11	0	0
T12	4866	0	0	0
T14	41168	61	0	0
T31	39985	47	0	0
T37	6266	33	0	0
T38	0	286	0	0
T51	0	91	0	0
T55	0	37	0	0
T56	0	156	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	13	0	0
T62	0	8	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1880	0	0
T5	34388	0	0	0
T11	3146	3	0	0
T12	4866	0	0	0
T14	41168	175	0	0
T31	39985	101	0	0
T34	2886	7	0	0
T37	0	11	0	0
T38	0	261	0	0
T51	0	137	0	0
T54	0	10	0	0
T55	0	16	0	0
T56	0	151	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1132	0	0
T14	41168	50	0	0
T31	39985	21	0	0
T34	2886	2	0	0
T37	6266	2	0	0
T38	293194	215	0	0
T51	0	23	0	0
T54	3943	6	0	0
T55	0	11	0	0
T56	0	63	0	0
T61	0	9	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1218	0	0
T5	34388	0	0	0
T11	3146	1	0	0
T12	4866	0	0	0
T14	41168	50	0	0
T31	39985	30	0	0
T34	2886	1	0	0
T37	0	1	0	0
T38	0	278	0	0
T51	0	28	0	0
T54	0	8	0	0
T55	0	47	0	0
T56	0	35	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1178	0	0
T5	34388	0	0	0
T11	3146	1	0	0
T12	4866	0	0	0
T14	41168	39	0	0
T31	39985	42	0	0
T37	6266	6	0	0
T38	0	264	0	0
T51	0	23	0	0
T54	0	16	0	0
T55	0	33	0	0
T56	0	48	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	13	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	969	0	0
T14	41168	49	0	0
T31	39985	19	0	0
T37	6266	4	0	0
T38	293194	311	0	0
T51	0	35	0	0
T54	3943	9	0	0
T55	0	12	0	0
T56	0	43	0	0
T61	0	16	0	0
T62	0	7	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1216	0	0
T14	41168	47	0	0
T31	39985	31	0	0
T38	293194	338	0	0
T51	0	18	0	0
T54	3943	7	0	0
T55	0	14	0	0
T56	0	48	0	0
T61	0	6	0	0
T62	0	2	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	239	0	0
T69	3715	0	0	0
T70	764	0	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	899	0	0
T14	41168	32	0	0
T31	39985	10	0	0
T38	293194	223	0	0
T51	0	21	0	0
T54	3943	10	0	0
T55	0	38	0	0
T56	0	58	0	0
T61	0	8	0	0
T62	0	7	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T69	3715	0	0	0
T70	764	0	0	0
T71	0	80	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1192	0	0
T5	34388	0	0	0
T11	3146	1	0	0
T12	4866	0	0	0
T14	41168	40	0	0
T31	39985	28	0	0
T34	2886	4	0	0
T38	0	299	0	0
T51	0	20	0	0
T54	0	4	0	0
T55	0	18	0	0
T56	0	52	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	8	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1034	0	0
T14	41168	38	0	0
T31	39985	17	0	0
T37	6266	4	0	0
T38	293194	245	0	0
T51	0	15	0	0
T54	3943	13	0	0
T55	0	10	0	0
T56	0	53	0	0
T61	0	11	0	0
T62	0	2	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1207	0	0
T5	34388	0	0	0
T11	3146	9	0	0
T12	4866	0	0	0
T14	41168	27	0	0
T31	39985	27	0	0
T34	2886	2	0	0
T38	0	325	0	0
T51	0	18	0	0
T54	0	13	0	0
T55	0	32	0	0
T56	0	32	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	3	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1013	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	43	0	0
T31	39985	22	0	0
T34	2886	1	0	0
T37	0	1	0	0
T38	0	257	0	0
T51	0	25	0	0
T54	0	7	0	0
T55	0	24	0	0
T56	0	43	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1912	0	0
T5	34388	0	0	0
T11	3146	16	0	0
T12	4866	0	0	0
T14	41168	121	0	0
T31	39985	75	0	0
T34	2886	2	0	0
T37	0	47	0	0
T38	0	255	0	0
T51	0	155	0	0
T54	0	9	0	0
T55	0	24	0	0
T56	0	224	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1198	0	0
T14	41168	46	0	0
T31	39985	25	0	0
T37	6266	3	0	0
T38	293194	284	0	0
T51	0	26	0	0
T54	3943	4	0	0
T55	0	28	0	0
T56	0	60	0	0
T61	0	14	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	245	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1797	0	0
T14	41168	129	0	0
T31	39985	85	0	0
T38	293194	295	0	0
T51	0	92	0	0
T54	3943	8	0	0
T55	0	30	0	0
T56	0	164	0	0
T61	0	74	0	0
T62	0	1	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	232	0	0
T69	3715	0	0	0
T70	764	0	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1951	0	0
T14	41168	179	0	0
T31	39985	58	0	0
T37	6266	37	0	0
T38	293194	298	0	0
T51	0	103	0	0
T54	3943	9	0	0
T55	0	20	0	0
T56	0	161	0	0
T61	0	29	0	0
T62	0	3	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1222	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	28	0	0
T31	39985	11	0	0
T34	2886	3	0	0
T37	0	9	0	0
T38	0	227	0	0
T51	0	42	0	0
T54	0	6	0	0
T55	0	30	0	0
T56	0	61	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	994	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	42	0	0
T31	39985	23	0	0
T34	2886	8	0	0
T37	0	4	0	0
T38	0	305	0	0
T51	0	20	0	0
T54	0	11	0	0
T55	0	36	0	0
T56	0	45	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	2010	0	0
T14	41168	97	0	0
T31	39985	83	0	0
T37	6266	14	0	0
T38	293194	257	0	0
T51	0	129	0	0
T54	3943	9	0	0
T55	0	37	0	0
T56	0	224	0	0
T61	0	36	0	0
T62	0	3	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1886	0	0
T5	34388	0	0	0
T11	3146	3	0	0
T12	4866	0	0	0
T14	41168	144	0	0
T31	39985	97	0	0
T34	2886	7	0	0
T37	0	11	0	0
T38	0	279	0	0
T51	0	71	0	0
T54	0	6	0	0
T55	0	11	0	0
T56	0	181	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1712	0	0
T5	34388	0	0	0
T11	3146	4	0	0
T12	4866	0	0	0
T14	41168	178	0	0
T31	39985	62	0	0
T34	2886	1	0	0
T37	0	31	0	0
T38	0	326	0	0
T51	0	123	0	0
T54	0	9	0	0
T55	0	17	0	0
T56	0	144	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1999	0	0
T5	34388	0	0	0
T11	3146	27	0	0
T12	4866	0	0	0
T14	41168	193	0	0
T31	39985	60	0	0
T37	6266	37	0	0
T38	0	261	0	0
T51	0	102	0	0
T54	0	9	0	0
T55	0	14	0	0
T56	0	179	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	31	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1971	0	0
T5	34388	0	0	0
T11	3146	7	0	0
T12	4866	0	0	0
T14	41168	164	0	0
T31	39985	89	0	0
T34	2886	1	0	0
T37	0	21	0	0
T38	0	249	0	0
T51	0	122	0	0
T54	0	12	0	0
T55	0	29	0	0
T56	0	170	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1914	0	0
T5	34388	0	0	0
T11	3146	1	0	0
T12	4866	0	0	0
T14	41168	93	0	0
T31	39985	57	0	0
T34	2886	3	0	0
T37	0	15	0	0
T38	0	314	0	0
T51	0	81	0	0
T54	0	9	0	0
T55	0	48	0	0
T56	0	232	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1859	0	0
T5	34388	0	0	0
T11	3146	13	0	0
T12	4866	0	0	0
T14	41168	194	0	0
T31	39985	72	0	0
T37	6266	30	0	0
T38	0	283	0	0
T51	0	117	0	0
T54	0	9	0	0
T55	0	8	0	0
T56	0	143	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	44	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1969	0	0
T5	34388	0	0	0
T11	3146	6	0	0
T12	4866	0	0	0
T14	41168	144	0	0
T31	39985	146	0	0
T37	6266	4	0	0
T38	0	245	0	0
T51	0	118	0	0
T54	0	7	0	0
T55	0	14	0	0
T56	0	121	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	19	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1827	0	0
T5	34388	0	0	0
T11	3146	7	0	0
T12	4866	0	0	0
T14	41168	150	0	0
T31	39985	58	0	0
T34	2886	4	0	0
T37	0	16	0	0
T38	0	275	0	0
T51	0	114	0	0
T54	0	6	0	0
T55	0	21	0	0
T56	0	161	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1560	0	0
T5	34388	0	0	0
T11	3146	8	0	0
T12	4866	0	0	0
T14	41168	161	0	0
T31	39985	75	0	0
T34	2886	5	0	0
T37	0	5	0	0
T38	0	271	0	0
T51	0	57	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	168	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1157	0	0
T14	41168	47	0	0
T31	39985	27	0	0
T34	2886	10	0	0
T37	6266	4	0	0
T38	293194	280	0	0
T51	0	34	0	0
T54	3943	7	0	0
T55	0	34	0	0
T56	0	65	0	0
T61	0	12	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1085	0	0
T14	41168	47	0	0
T31	39985	21	0	0
T34	2886	8	0	0
T37	6266	2	0	0
T38	293194	282	0	0
T51	0	26	0	0
T54	3943	6	0	0
T55	0	40	0	0
T56	0	30	0	0
T61	0	11	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1136	0	0
T14	41168	44	0	0
T31	39985	22	0	0
T34	2886	4	0	0
T38	293194	265	0	0
T51	0	19	0	0
T54	3943	6	0	0
T55	0	9	0	0
T56	0	44	0	0
T61	0	5	0	0
T62	0	2	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T69	3715	0	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1209	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	38	0	0
T31	39985	7	0	0
T38	293194	288	0	0
T51	0	9	0	0
T54	0	12	0	0
T55	0	29	0	0
T56	0	27	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	13	0	0
T62	0	3	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	926	0	0
T14	41168	37	0	0
T31	39985	33	0	0
T37	6266	13	0	0
T38	293194	275	0	0
T51	0	19	0	0
T54	3943	2	0	0
T55	0	35	0	0
T56	0	33	0	0
T61	0	5	0	0
T62	0	7	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1179	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	46	0	0
T31	39985	28	0	0
T34	2886	6	0	0
T37	0	11	0	0
T38	0	307	0	0
T51	0	15	0	0
T54	0	7	0	0
T55	0	2	0	0
T56	0	55	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1265	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	54	0	0
T31	39985	24	0	0
T34	2886	8	0	0
T38	0	308	0	0
T51	0	5	0	0
T54	0	9	0	0
T55	0	8	0	0
T56	0	32	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	6	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1113	0	0
T5	34388	0	0	0
T11	3146	10	0	0
T12	4866	0	0	0
T14	41168	38	0	0
T31	39985	17	0	0
T34	2886	6	0	0
T37	0	9	0	0
T38	0	294	0	0
T51	0	31	0	0
T54	0	2	0	0
T55	0	11	0	0
T56	0	33	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	957	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	51	0	0
T31	39985	12	0	0
T37	6266	5	0	0
T38	0	308	0	0
T51	0	16	0	0
T54	0	4	0	0
T55	0	25	0	0
T56	0	66	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	5	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1060	0	0
T14	41168	38	0	0
T31	39985	25	0	0
T34	2886	2	0	0
T38	293194	226	0	0
T51	0	28	0	0
T54	3943	11	0	0
T56	0	42	0	0
T61	0	12	0	0
T62	0	6	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	254	0	0
T69	3715	0	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1573	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	230	0	0
T31	39985	27	0	0
T34	2886	2	0	0
T37	0	29	0	0
T38	0	276	0	0
T51	0	53	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	164	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	892	0	0
T5	34388	0	0	0
T11	3146	8	0	0
T12	4866	0	0	0
T14	41168	34	0	0
T31	39985	20	0	0
T37	6266	9	0	0
T38	0	249	0	0
T51	0	29	0	0
T54	0	13	0	0
T55	0	3	0	0
T56	0	93	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	12	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1870	0	0
T5	34388	0	0	0
T11	3146	4	0	0
T12	4866	0	0	0
T14	41168	68	0	0
T31	39985	106	0	0
T37	6266	5	0	0
T38	0	297	0	0
T51	0	135	0	0
T54	0	12	0	0
T55	0	18	0	0
T56	0	125	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	45	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1824	0	0
T5	34388	0	0	0
T11	3146	12	0	0
T12	4866	0	0	0
T14	41168	142	0	0
T31	39985	93	0	0
T34	2886	1	0	0
T37	0	32	0	0
T38	0	227	0	0
T51	0	131	0	0
T54	0	8	0	0
T55	0	27	0	0
T56	0	266	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	815	0	0
T5	34388	0	0	0
T11	3146	7	0	0
T12	4866	0	0	0
T14	41168	42	0	0
T31	39985	25	0	0
T37	6266	5	0	0
T38	0	261	0	0
T51	0	14	0	0
T54	0	8	0	0
T55	0	2	0	0
T56	0	31	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	10	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1181	0	0
T14	41168	41	0	0
T31	39985	31	0	0
T34	2886	6	0	0
T37	6266	1	0	0
T38	293194	270	0	0
T51	0	14	0	0
T54	3943	15	0	0
T55	0	31	0	0
T56	0	43	0	0
T61	0	13	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1134	0	0
T14	41168	35	0	0
T31	39985	13	0	0
T34	2886	1	0	0
T38	293194	321	0	0
T51	0	12	0	0
T54	3943	6	0	0
T55	0	32	0	0
T56	0	39	0	0
T61	0	10	0	0
T62	0	4	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T69	3715	0	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1641	0	0
T5	34388	0	0	0
T11	3146	23	0	0
T12	4866	0	0	0
T14	41168	126	0	0
T31	39985	94	0	0
T37	6266	20	0	0
T38	0	256	0	0
T51	0	80	0	0
T54	0	9	0	0
T55	0	22	0	0
T56	0	148	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	17	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1182	0	0
T14	41168	37	0	0
T31	39985	8	0	0
T37	6266	8	0	0
T38	293194	301	0	0
T51	0	15	0	0
T54	3943	8	0	0
T55	0	43	0	0
T56	0	71	0	0
T61	0	4	0	0
T62	0	8	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1343	0	0
T5	34388	0	0	0
T11	3146	3	0	0
T12	4866	0	0	0
T14	41168	65	0	0
T31	39985	39	0	0
T37	6266	1	0	0
T38	0	277	0	0
T51	0	42	0	0
T54	0	15	0	0
T55	0	35	0	0
T56	0	35	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	18	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	910	0	0
T14	41168	42	0	0
T31	39985	9	0	0
T37	6266	6	0	0
T38	293194	258	0	0
T51	0	18	0	0
T54	3943	12	0	0
T55	0	20	0	0
T56	0	55	0	0
T61	0	3	0	0
T62	0	6	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1223	0	0
T5	34388	0	0	0
T11	3146	17	0	0
T12	4866	0	0	0
T14	41168	54	0	0
T31	39985	19	0	0
T34	2886	2	0	0
T38	0	215	0	0
T51	0	30	0	0
T54	0	9	0	0
T55	0	22	0	0
T56	0	92	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1958	0	0
T5	34388	0	0	0
T11	3146	26	0	0
T12	4866	0	0	0
T14	41168	222	0	0
T31	39985	96	0	0
T34	2886	10	0	0
T37	0	7	0	0
T38	0	311	0	0
T51	0	74	0	0
T54	0	8	0	0
T55	0	15	0	0
T56	0	200	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	947	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	36	0	0
T31	39985	34	0	0
T34	2886	4	0	0
T37	0	9	0	0
T38	0	277	0	0
T51	0	19	0	0
T54	0	4	0	0
T55	0	26	0	0
T56	0	55	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1036	0	0
T14	41168	76	0	0
T31	39985	13	0	0
T34	2886	2	0	0
T37	6266	9	0	0
T38	293194	298	0	0
T51	0	45	0	0
T54	3943	8	0	0
T55	0	18	0	0
T56	0	78	0	0
T61	0	5	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1161	0	0
T5	34388	0	0	0
T11	3146	6	0	0
T12	4866	0	0	0
T14	41168	59	0	0
T31	39985	54	0	0
T34	2886	4	0	0
T37	0	21	0	0
T38	0	196	0	0
T51	0	46	0	0
T54	0	7	0	0
T55	0	32	0	0
T56	0	33	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1304	0	0
T5	34388	0	0	0
T11	3146	9	0	0
T12	4866	0	0	0
T14	41168	74	0	0
T31	39985	23	0	0
T38	293194	255	0	0
T51	0	54	0	0
T54	0	13	0	0
T55	0	13	0	0
T56	0	106	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	23	0	0
T62	0	3	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1255	0	0
T5	34388	0	0	0
T11	3146	3	0	0
T12	4866	0	0	0
T14	41168	40	0	0
T31	39985	35	0	0
T34	2886	6	0	0
T38	0	369	0	0
T51	0	26	0	0
T54	0	11	0	0
T55	0	6	0	0
T56	0	60	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	11	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1187	0	0
T5	34388	0	0	0
T11	3146	1	0	0
T12	4866	0	0	0
T14	41168	70	0	0
T31	39985	53	0	0
T37	6266	8	0	0
T38	0	197	0	0
T51	0	26	0	0
T54	0	7	0	0
T55	0	8	0	0
T56	0	71	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	7	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1276	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	43	0	0
T31	39985	31	0	0
T37	6266	17	0	0
T38	0	227	0	0
T51	0	29	0	0
T54	0	15	0	0
T55	0	44	0	0
T56	0	70	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	18	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1232	0	0
T14	41168	65	0	0
T31	39985	23	0	0
T37	6266	5	0	0
T38	293194	249	0	0
T51	0	44	0	0
T54	3943	9	0	0
T55	0	18	0	0
T56	0	78	0	0
T61	0	12	0	0
T62	0	7	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1630	0	0
T14	41168	164	0	0
T31	39985	81	0	0
T34	2886	3	0	0
T37	6266	10	0	0
T38	293194	277	0	0
T51	0	59	0	0
T54	3943	7	0	0
T55	0	18	0	0
T56	0	145	0	0
T61	0	46	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1807	0	0
T14	41168	138	0	0
T31	39985	108	0	0
T37	6266	21	0	0
T38	293194	291	0	0
T51	0	95	0	0
T54	3943	5	0	0
T55	0	24	0	0
T56	0	108	0	0
T61	0	25	0	0
T62	0	3	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1622	0	0
T14	41168	168	0	0
T31	39985	50	0	0
T34	2886	8	0	0
T37	6266	27	0	0
T38	293194	247	0	0
T51	0	79	0	0
T54	3943	10	0	0
T55	0	7	0	0
T56	0	117	0	0
T61	0	7	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1759	0	0
T5	34388	0	0	0
T11	3146	26	0	0
T12	4866	0	0	0
T14	41168	205	0	0
T31	39985	104	0	0
T34	2886	5	0	0
T37	0	14	0	0
T38	0	300	0	0
T51	0	52	0	0
T54	0	14	0	0
T55	0	19	0	0
T56	0	190	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1663	0	0
T14	41168	211	0	0
T31	39985	10	0	0
T37	6266	10	0	0
T38	293194	259	0	0
T51	0	84	0	0
T54	3943	9	0	0
T55	0	11	0	0
T56	0	138	0	0
T61	0	11	0	0
T62	0	6	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1773	0	0
T5	34388	0	0	0
T11	3146	11	0	0
T12	4866	0	0	0
T14	41168	185	0	0
T31	39985	81	0	0
T37	6266	5	0	0
T38	0	199	0	0
T51	0	88	0	0
T54	0	8	0	0
T55	0	28	0	0
T56	0	130	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	10	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1868	0	0
T5	34388	0	0	0
T11	3146	5	0	0
T12	4866	0	0	0
T14	41168	94	0	0
T31	39985	85	0	0
T37	6266	20	0	0
T38	0	298	0	0
T51	0	149	0	0
T54	0	6	0	0
T55	0	38	0	0
T56	0	206	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	31	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1946	0	0
T5	34388	0	0	0
T11	3146	17	0	0
T12	4866	0	0	0
T14	41168	166	0	0
T31	39985	80	0	0
T37	6266	8	0	0
T38	0	294	0	0
T51	0	52	0	0
T54	0	14	0	0
T55	0	31	0	0
T56	0	187	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	12	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	328	0	0
T14	41168	0	0	0
T31	39985	0	0	0
T34	2886	4	0	0
T54	3943	7	0	0
T55	17932	6	0	0
T62	0	6	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	266	0	0
T69	3715	0	0	0
T70	764	0	0	0
T72	0	13	0	0
T73	0	5	0	0
T74	0	4	0	0
T75	0	13	0	0
T76	0	4	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1168	0	0
T14	41168	37	0	0
T31	39985	9	0	0
T38	293194	256	0	0
T51	0	3	0	0
T54	3943	15	0	0
T55	0	46	0	0
T56	0	43	0	0
T61	0	13	0	0
T62	0	3	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T68	0	256	0	0
T69	3715	0	0	0
T70	764	0	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1203	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	40	0	0
T31	39985	20	0	0
T34	2886	3	0	0
T37	0	3	0	0
T38	0	313	0	0
T51	0	19	0	0
T54	0	8	0	0
T55	0	20	0	0
T56	0	31	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1065	0	0
T5	34388	0	0	0
T11	3146	6	0	0
T12	4866	0	0	0
T14	41168	29	0	0
T31	39985	20	0	0
T37	6266	6	0	0
T38	0	293	0	0
T51	0	14	0	0
T54	0	6	0	0
T55	0	20	0	0
T56	0	43	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T62	0	2	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1177	0	0
T14	41168	39	0	0
T31	39985	37	0	0
T37	6266	3	0	0
T38	293194	304	0	0
T51	0	16	0	0
T54	3943	3	0	0
T55	0	35	0	0
T56	0	56	0	0
T61	0	9	0	0
T62	0	5	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1198	0	0
T5	34388	0	0	0
T11	3146	2	0	0
T12	4866	0	0	0
T14	41168	33	0	0
T31	39985	20	0	0
T37	6266	16	0	0
T38	0	319	0	0
T51	0	22	0	0
T54	0	5	0	0
T55	0	34	0	0
T56	0	66	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	5	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1071	0	0
T5	34388	0	0	0
T11	3146	8	0	0
T12	4866	0	0	0
T14	41168	38	0	0
T31	39985	12	0	0
T37	6266	6	0	0
T38	0	257	0	0
T51	0	27	0	0
T54	0	6	0	0
T55	0	12	0	0
T56	0	40	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T62	0	5	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1126	0	0
T14	41168	45	0	0
T31	39985	26	0	0
T34	2886	3	0	0
T37	6266	8	0	0
T38	293194	272	0	0
T51	0	24	0	0
T54	3943	6	0	0
T55	0	16	0	0
T56	0	20	0	0
T61	0	10	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	890	0	0
T14	41168	53	0	0
T31	39985	18	0	0
T37	6266	9	0	0
T38	293194	275	0	0
T51	0	30	0	0
T54	3943	10	0	0
T55	0	6	0	0
T56	0	34	0	0
T61	0	11	0	0
T63	2369	0	0	0
T64	1203	0	0	0
T65	1105	0	0	0
T66	14661	0	0	0
T67	2152	0	0	0
T71	0	90	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2326356	1082	0	0
T5	34388	0	0	0
T11	3146	6	0	0
T12	4866	0	0	0
T14	41168	36	0	0
T31	39985	22	0	0
T37	6266	2	0	0
T38	0	246	0	0
T51	0	10	0	0
T54	0	2	0	0
T55	0	19	0	0
T56	0	64	0	0
T57	1215	0	0	0
T58	1431	0	0	0
T59	1597	0	0	0
T60	1461	0	0	0
T61	0	7	0	0