Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
55.82 51.96 51.79 49.37 0.00 66.43 99.33 71.84


Total tests in report: 211
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
44.11 44.11 49.65 49.65 42.91 42.91 59.90 59.90 0.00 0.00 58.21 58.21 78.65 78.65 19.47 19.47 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.535882417
52.45 8.34 50.78 1.12 49.11 6.20 63.81 3.91 0.00 0.00 64.09 5.88 97.75 19.10 41.64 22.17 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2279744009
54.33 1.88 51.34 0.57 49.30 0.19 66.59 2.78 0.00 0.00 64.09 0.00 97.75 0.00 51.25 9.61 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2213791585
55.49 1.16 51.56 0.22 49.99 0.69 67.78 1.20 0.00 0.00 64.74 0.65 97.75 0.00 56.61 5.36 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.683871529
56.25 0.76 51.95 0.39 51.43 1.44 68.18 0.40 0.00 0.00 66.43 1.69 97.75 0.00 57.99 1.38 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2685229894
56.81 0.56 51.95 0.00 51.43 0.00 68.78 0.60 0.00 0.00 66.43 0.00 99.10 1.35 60.00 2.01 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4131475000
57.19 0.38 51.95 0.00 51.43 0.00 69.27 0.49 0.00 0.00 66.43 0.00 99.10 0.00 62.14 2.14 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1677136719
57.51 0.32 51.95 0.00 51.58 0.15 69.65 0.38 0.00 0.00 66.43 0.00 99.10 0.00 63.85 1.71 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2325519797
57.75 0.24 51.95 0.00 51.74 0.16 69.92 0.27 0.00 0.00 66.43 0.00 99.10 0.00 65.10 1.25 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3203417537
57.94 0.19 51.95 0.00 51.75 0.01 70.38 0.47 0.00 0.00 66.43 0.00 99.10 0.00 65.99 0.89 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3146976785
58.11 0.17 51.95 0.00 51.75 0.00 70.52 0.13 0.00 0.00 66.43 0.00 99.10 0.00 67.04 1.05 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2517625786
58.24 0.13 51.95 0.00 51.75 0.00 70.76 0.24 0.00 0.00 66.43 0.00 99.10 0.00 67.70 0.66 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.451411765
58.34 0.10 51.95 0.00 51.75 0.00 71.25 0.49 0.00 0.00 66.43 0.00 99.10 0.00 67.89 0.20 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3858924109
58.44 0.10 51.95 0.00 51.75 0.00 71.36 0.11 0.00 0.00 66.43 0.00 99.10 0.00 68.45 0.56 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1363542477
58.52 0.08 51.95 0.00 51.75 0.00 71.43 0.07 0.00 0.00 66.43 0.00 99.10 0.00 68.95 0.49 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2329024860
58.58 0.07 51.95 0.00 51.75 0.00 71.47 0.04 0.00 0.00 66.43 0.00 99.10 0.00 69.38 0.43 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3434538704
58.64 0.05 51.95 0.00 51.77 0.02 71.47 0.00 0.00 0.00 66.43 0.00 99.10 0.00 69.74 0.36 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1648453427
58.68 0.05 51.95 0.00 51.77 0.00 71.47 0.00 0.00 0.00 66.43 0.00 99.33 0.22 69.84 0.10 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2611820192
58.73 0.04 51.95 0.00 51.77 0.00 71.51 0.04 0.00 0.00 66.43 0.00 99.33 0.00 70.10 0.26 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1048457724
58.77 0.04 51.95 0.00 51.77 0.00 71.56 0.04 0.00 0.00 66.43 0.00 99.33 0.00 70.33 0.23 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3668556536
58.80 0.03 51.95 0.00 51.77 0.00 71.58 0.02 0.00 0.00 66.43 0.00 99.33 0.00 70.53 0.20 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3181525630
58.83 0.03 51.95 0.00 51.77 0.00 71.65 0.07 0.00 0.00 66.43 0.00 99.33 0.00 70.66 0.13 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4275854965
58.85 0.03 51.95 0.00 51.77 0.00 71.65 0.00 0.00 0.00 66.43 0.00 99.33 0.00 70.86 0.20 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1255874975
58.88 0.02 51.95 0.00 51.77 0.00 71.67 0.02 0.00 0.00 66.43 0.00 99.33 0.00 70.99 0.13 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2229217610
58.90 0.02 51.95 0.00 51.77 0.00 71.67 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.12 0.13 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4287504031
58.91 0.02 51.95 0.00 51.77 0.00 71.76 0.09 0.00 0.00 66.43 0.00 99.33 0.00 71.15 0.03 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3735305409
58.93 0.01 51.95 0.00 51.77 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.25 0.10 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3094828630
58.94 0.01 51.95 0.00 51.77 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.35 0.10 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1282068783
58.96 0.01 51.95 0.00 51.77 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.45 0.10 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.15422125
58.96 0.01 51.95 0.00 51.77 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.51 0.07 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1002280155
58.97 0.01 51.95 0.00 51.77 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.58 0.07 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1113660357
58.98 0.01 51.95 0.00 51.77 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.64 0.07 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3707345103
58.99 0.01 51.96 0.01 51.78 0.01 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.68 0.03 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.698102827
59.00 0.01 51.96 0.00 51.78 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.71 0.03 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3642348298
59.00 0.01 51.96 0.00 51.78 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.74 0.03 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1952379873
59.00 0.01 51.96 0.00 51.78 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.78 0.03 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3942568623
59.01 0.01 51.96 0.00 51.78 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.81 0.03 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.474093514
59.01 0.01 51.96 0.00 51.78 0.00 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.84 0.03 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.614091211
59.02 0.01 51.96 0.00 51.79 0.01 71.76 0.00 0.00 0.00 66.43 0.00 99.33 0.00 71.84 0.00 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.812029932

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3897638723
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1256630091
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1365775346
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2998528242
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1029136336
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.348152035
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4090891858
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3073672173
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.434991570
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2733002028
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1520551644
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2455327408
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1924654667
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3076594742
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1356236355
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2908386946
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3009325825
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3617122758
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3376897910
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.24350839
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.473645238
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3296285581
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.699741005
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2818083945
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1731613515
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3349754789
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1302619445
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.591010569
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.820264016
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2844043798
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4144574982
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2780097083
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1952498383
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1866591792
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3304005237
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4022902253
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.959277764
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3905998577
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3030249412
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.785546796
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.922095281
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3442922303
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3215752488
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4105909413
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1318112476
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2262961940
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.907683244
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4238409752
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.414874216
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3804281156
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2761042977
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.791758740
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.291471038
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1458573128
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4270389299
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2043972105
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.476031199
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1792341459
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3586349285
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.648783720
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1190175014
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1672083687
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1106455939
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1115291493
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4033420212
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3491474502
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3355330339
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4054469650
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1904196833
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.600624505
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.898254242
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1740145439
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2539152569
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3694650668
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.734515190
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1783178205
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1791190168
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.353436133
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2264205076
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1046202738
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4162957711
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1452176803
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2623766665
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3295329205
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.120546407
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3089181432
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4237873251
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.593113646
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.974005448
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.554120136
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1125941123
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1712823235
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3791412489
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3957879419
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.791403907
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1916753634
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3553468474
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1745447367
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3045190695
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3995599677
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1108455576
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2051809473
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3527774030
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.872786
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2687117467
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3358727592
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2358412605
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.559524221
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1305236058
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3347295805
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3563377069
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.802540383
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1668153883
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2209903132
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2026892894
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4020112342
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.570450526
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3857378066
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3513821715
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1212826463
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3623523918
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3071906535
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4141710236
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2595447343
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1090778756
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.392586064
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4280422420
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3996759944
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.56240224
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2043589137
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3871226504
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3614282315
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2368970841
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1062909425
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1206081104
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2637883350
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2202245528
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2713970276
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2412847754
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2592520075
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.596670015
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.142292294
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1688144772
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2931497069
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4054727106
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4156209152
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3886051806
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2463423725
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1431118254
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1534478610
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3129241449
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1905152316
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2062586188
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.818552902
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4019834166
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2559949304
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4294019878
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3894816197
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2857345895
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2657629030
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2310405992
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1423066199
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2702472588
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.157522051
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3928801849
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2336807011
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2972464735
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1178604569
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3861147747
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2790805604
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3431731431
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1344427218



Total test records in report: 211
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.348152035 Jan 10 12:59:53 PM PST 24 Jan 10 01:01:37 PM PST 24 17445900 ps
T2 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.535882417 Jan 10 01:00:11 PM PST 24 Jan 10 01:01:53 PM PST 24 46224600 ps
T3 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4054727106 Jan 10 01:00:13 PM PST 24 Jan 10 01:02:01 PM PST 24 17444800 ps
T10 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3355330339 Jan 10 01:00:19 PM PST 24 Jan 10 01:01:58 PM PST 24 467825000 ps
T7 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.683871529 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:55 PM PST 24 16001600 ps
T13 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3347295805 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:52 PM PST 24 36709100 ps
T8 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1731613515 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:22 PM PST 24 33974600 ps
T9 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1677136719 Jan 10 01:00:10 PM PST 24 Jan 10 01:02:22 PM PST 24 93161400 ps
T4 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4144574982 Jan 10 01:00:13 PM PST 24 Jan 10 01:02:20 PM PST 24 492229300 ps
T16 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4020112342 Jan 10 01:00:36 PM PST 24 Jan 10 01:02:05 PM PST 24 17415100 ps
T29 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2637883350 Jan 10 01:00:52 PM PST 24 Jan 10 01:02:38 PM PST 24 24003500 ps
T77 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1206081104 Jan 10 01:01:09 PM PST 24 Jan 10 01:02:52 PM PST 24 46436000 ps
T135 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.907683244 Jan 10 01:00:09 PM PST 24 Jan 10 01:02:06 PM PST 24 11761000 ps
T11 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.142292294 Jan 10 01:00:11 PM PST 24 Jan 10 01:01:51 PM PST 24 130913900 ps
T12 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2213791585 Jan 10 01:00:07 PM PST 24 Jan 10 01:01:55 PM PST 24 49660000 ps
T57 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.559524221 Jan 10 01:00:01 PM PST 24 Jan 10 01:01:48 PM PST 24 24349000 ps
T5 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2685229894 Jan 10 01:00:10 PM PST 24 Jan 10 01:17:00 PM PST 24 343906300 ps
T58 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3431731431 Jan 10 01:00:51 PM PST 24 Jan 10 01:02:27 PM PST 24 14614100 ps
T59 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4090891858 Jan 10 01:00:12 PM PST 24 Jan 10 01:02:36 PM PST 24 16000000 ps
T60 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.791758740 Jan 10 01:00:23 PM PST 24 Jan 10 01:02:17 PM PST 24 14921300 ps
T21 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4131475000 Jan 10 01:00:02 PM PST 24 Jan 10 01:01:43 PM PST 24 25908800 ps
T15 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.820264016 Jan 10 01:00:14 PM PST 24 Jan 10 01:02:26 PM PST 24 277973800 ps
T41 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4054469650 Jan 10 01:00:23 PM PST 24 Jan 10 01:02:44 PM PST 24 14036300 ps
T42 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1458573128 Jan 10 01:00:16 PM PST 24 Jan 10 01:01:59 PM PST 24 77976900 ps
T20 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1363542477 Jan 10 01:00:03 PM PST 24 Jan 10 01:01:47 PM PST 24 47976900 ps
T43 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2329024860 Jan 10 01:00:11 PM PST 24 Jan 10 01:02:25 PM PST 24 28144400 ps
T17 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3434538704 Jan 10 01:00:15 PM PST 24 Jan 10 01:02:46 PM PST 24 371578700 ps
T18 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3553468474 Jan 10 01:00:31 PM PST 24 Jan 10 01:02:04 PM PST 24 30868000 ps
T32 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2539152569 Jan 10 01:00:26 PM PST 24 Jan 10 01:02:10 PM PST 24 49567700 ps
T44 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.120546407 Jan 10 01:01:04 PM PST 24 Jan 10 01:02:37 PM PST 24 40745700 ps
T6 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.818552902 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:04 PM PST 24 41568000 ps
T33 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1712823235 Jan 10 01:00:01 PM PST 24 Jan 10 01:02:09 PM PST 24 384567800 ps
T136 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1952498383 Jan 10 01:00:47 PM PST 24 Jan 10 01:02:11 PM PST 24 29393400 ps
T89 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3045190695 Jan 10 01:01:04 PM PST 24 Jan 10 01:02:42 PM PST 24 84696300 ps
T137 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2931497069 Jan 10 01:00:13 PM PST 24 Jan 10 01:02:46 PM PST 24 18795200 ps
T138 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1302619445 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:46 PM PST 24 83869600 ps
T90 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2517625786 Jan 10 01:00:05 PM PST 24 Jan 10 01:02:07 PM PST 24 14922700 ps
T34 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2687117467 Jan 10 01:00:04 PM PST 24 Jan 10 01:01:59 PM PST 24 64092000 ps
T14 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2279744009 Jan 10 01:00:15 PM PST 24 Jan 10 01:09:35 PM PST 24 8234077400 ps
T31 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3886051806 Jan 10 01:00:10 PM PST 24 Jan 10 01:09:37 PM PST 24 399880700 ps
T139 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2780097083 Jan 10 01:00:16 PM PST 24 Jan 10 01:01:53 PM PST 24 60707200 ps
T35 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.291471038 Jan 10 01:00:29 PM PST 24 Jan 10 01:03:06 PM PST 24 448664900 ps
T19 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1178604569 Jan 10 01:00:06 PM PST 24 Jan 10 01:02:18 PM PST 24 53304300 ps
T140 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3295329205 Jan 10 01:00:36 PM PST 24 Jan 10 01:02:24 PM PST 24 23615900 ps
T86 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2761042977 Jan 10 01:00:24 PM PST 24 Jan 10 01:02:40 PM PST 24 673972800 ps
T102 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.451411765 Jan 10 01:00:56 PM PST 24 Jan 10 01:02:41 PM PST 24 45868800 ps
T22 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4105909413 Jan 10 01:00:14 PM PST 24 Jan 10 01:02:45 PM PST 24 37030300 ps
T91 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1255874975 Jan 10 01:00:31 PM PST 24 Jan 10 01:02:02 PM PST 24 15047800 ps
T96 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1916753634 Jan 10 01:00:36 PM PST 24 Jan 10 01:02:44 PM PST 24 93903300 ps
T141 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2702472588 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:55 PM PST 24 31501700 ps
T23 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3146976785 Jan 10 01:00:20 PM PST 24 Jan 10 01:02:25 PM PST 24 38680200 ps
T142 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4294019878 Jan 10 01:00:14 PM PST 24 Jan 10 01:01:51 PM PST 24 32821200 ps
T143 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3073672173 Jan 10 01:00:00 PM PST 24 Jan 10 01:02:08 PM PST 24 159391200 ps
T24 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2325519797 Jan 10 12:59:56 PM PST 24 Jan 10 01:01:45 PM PST 24 57306700 ps
T105 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3707345103 Jan 10 01:00:36 PM PST 24 Jan 10 01:02:15 PM PST 24 29893700 ps
T25 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3203417537 Jan 10 12:59:57 PM PST 24 Jan 10 01:01:50 PM PST 24 195949900 ps
T94 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2592520075 Jan 10 01:00:36 PM PST 24 Jan 10 01:02:44 PM PST 24 14457500 ps
T95 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2713970276 Jan 10 01:01:03 PM PST 24 Jan 10 01:02:37 PM PST 24 85211200 ps
T144 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3129241449 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:49 PM PST 24 17668300 ps
T36 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.15422125 Jan 10 01:00:01 PM PST 24 Jan 10 01:01:47 PM PST 24 17680200 ps
T26 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1046202738 Jan 10 01:01:14 PM PST 24 Jan 10 01:02:55 PM PST 24 23637700 ps
T27 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.699741005 Jan 10 01:00:11 PM PST 24 Jan 10 01:02:16 PM PST 24 44165100 ps
T145 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3563377069 Jan 10 01:00:04 PM PST 24 Jan 10 01:01:46 PM PST 24 14526800 ps
T97 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2368970841 Jan 10 01:00:35 PM PST 24 Jan 10 01:02:36 PM PST 24 16166100 ps
T146 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3957879419 Jan 10 01:00:02 PM PST 24 Jan 10 01:01:53 PM PST 24 40234800 ps
T88 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3358727592 Jan 10 01:00:06 PM PST 24 Jan 10 01:02:15 PM PST 24 119846600 ps
T147 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.922095281 Jan 10 01:00:17 PM PST 24 Jan 10 01:02:27 PM PST 24 91134300 ps
T148 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1905152316 Jan 10 01:00:11 PM PST 24 Jan 10 01:01:51 PM PST 24 14934800 ps
T37 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2998528242 Jan 10 01:00:03 PM PST 24 Jan 10 01:01:59 PM PST 24 179269700 ps
T63 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4141710236 Jan 10 01:00:17 PM PST 24 Jan 10 01:02:43 PM PST 24 35100600 ps
T38 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2455327408 Jan 10 01:00:03 PM PST 24 Jan 10 01:02:53 PM PST 24 8385404600 ps
T64 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2733002028 Jan 10 12:59:57 PM PST 24 Jan 10 01:01:49 PM PST 24 23133100 ps
T54 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.698102827 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:57 PM PST 24 157769600 ps
T65 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4238409752 Jan 10 01:00:12 PM PST 24 Jan 10 01:02:02 PM PST 24 11521100 ps
T66 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1688144772 Jan 10 01:00:10 PM PST 24 Jan 10 01:02:28 PM PST 24 152503000 ps
T67 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1365775346 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:59 PM PST 24 43917300 ps
T69 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1924654667 Jan 10 01:00:06 PM PST 24 Jan 10 01:02:50 PM PST 24 309991100 ps
T70 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1106455939 Jan 10 01:00:24 PM PST 24 Jan 10 01:02:46 PM PST 24 26313000 ps
T55 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1423066199 Jan 10 01:00:09 PM PST 24 Jan 10 01:02:10 PM PST 24 512918900 ps
T149 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.802540383 Jan 10 01:00:03 PM PST 24 Jan 10 01:01:42 PM PST 24 17157200 ps
T150 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.56240224 Jan 10 01:00:22 PM PST 24 Jan 10 01:02:38 PM PST 24 21701000 ps
T87 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.872786 Jan 10 01:00:06 PM PST 24 Jan 10 01:03:34 PM PST 24 2632450700 ps
T151 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.785546796 Jan 10 01:00:14 PM PST 24 Jan 10 01:01:55 PM PST 24 744838100 ps
T93 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3995599677 Jan 10 01:01:02 PM PST 24 Jan 10 01:02:42 PM PST 24 34570200 ps
T100 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3491474502 Jan 10 01:00:24 PM PST 24 Jan 10 01:02:41 PM PST 24 158536800 ps
T51 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3928801849 Jan 10 01:00:13 PM PST 24 Jan 10 01:08:43 PM PST 24 797900000 ps
T152 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3527774030 Jan 10 01:00:03 PM PST 24 Jan 10 01:02:35 PM PST 24 841535300 ps
T153 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2790805604 Jan 10 01:00:47 PM PST 24 Jan 10 01:02:12 PM PST 24 11733700 ps
T28 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1282068783 Jan 10 01:00:43 PM PST 24 Jan 10 01:02:12 PM PST 24 95946700 ps
T50 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1344427218 Jan 10 01:00:12 PM PST 24 Jan 10 01:16:45 PM PST 24 763419700 ps
T106 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.648783720 Jan 10 01:00:22 PM PST 24 Jan 10 01:02:06 PM PST 24 28256400 ps
T30 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3942568623 Jan 10 01:00:24 PM PST 24 Jan 10 01:02:38 PM PST 24 36082000 ps
T80 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3735305409 Jan 10 01:00:44 PM PST 24 Jan 10 01:16:49 PM PST 24 1405454000 ps
T154 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.157522051 Jan 10 01:00:19 PM PST 24 Jan 10 01:02:09 PM PST 24 14994200 ps
T155 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2559949304 Jan 10 01:00:53 PM PST 24 Jan 10 01:02:55 PM PST 24 155581000 ps
T82 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3858924109 Jan 10 01:00:15 PM PST 24 Jan 10 01:16:18 PM PST 24 354108300 ps
T52 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.554120136 Jan 10 01:00:03 PM PST 24 Jan 10 01:01:56 PM PST 24 26718100 ps
T156 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3376897910 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:48 PM PST 24 40193800 ps
T111 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3668556536 Jan 10 01:00:50 PM PST 24 Jan 10 01:02:27 PM PST 24 53127600 ps
T157 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3623523918 Jan 10 01:00:09 PM PST 24 Jan 10 01:02:25 PM PST 24 423573400 ps
T114 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.474093514 Jan 10 01:00:31 PM PST 24 Jan 10 01:02:04 PM PST 24 17904300 ps
T104 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2229217610 Jan 10 01:00:32 PM PST 24 Jan 10 01:02:15 PM PST 24 68593800 ps
T39 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3009325825 Jan 10 01:00:02 PM PST 24 Jan 10 01:02:27 PM PST 24 17879900 ps
T48 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2463423725 Jan 10 01:00:16 PM PST 24 Jan 10 01:01:58 PM PST 24 33687900 ps
T158 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.591010569 Jan 10 01:00:17 PM PST 24 Jan 10 01:02:12 PM PST 24 14859100 ps
T83 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3871226504 Jan 10 01:00:18 PM PST 24 Jan 10 01:08:03 PM PST 24 674623500 ps
T85 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.791403907 Jan 10 01:00:03 PM PST 24 Jan 10 01:09:02 PM PST 24 366233800 ps
T159 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1672083687 Jan 10 01:00:21 PM PST 24 Jan 10 01:02:04 PM PST 24 55154600 ps
T53 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.812029932 Jan 10 01:00:21 PM PST 24 Jan 10 01:16:35 PM PST 24 1353781100 ps
T160 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2262961940 Jan 10 01:00:14 PM PST 24 Jan 10 01:02:38 PM PST 24 486993300 ps
T103 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3094828630 Jan 10 01:00:01 PM PST 24 Jan 10 01:01:48 PM PST 24 27542200 ps
T161 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1431118254 Jan 10 01:00:06 PM PST 24 Jan 10 01:02:04 PM PST 24 104453900 ps
T162 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4270389299 Jan 10 01:00:16 PM PST 24 Jan 10 01:01:51 PM PST 24 11476800 ps
T115 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1108455576 Jan 10 01:00:31 PM PST 24 Jan 10 01:02:42 PM PST 24 18388400 ps
T113 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1745447367 Jan 10 01:00:36 PM PST 24 Jan 10 01:02:05 PM PST 24 17748800 ps
T163 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3905998577 Jan 10 01:00:15 PM PST 24 Jan 10 01:01:53 PM PST 24 24885900 ps
T108 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3614282315 Jan 10 01:00:46 PM PST 24 Jan 10 01:02:17 PM PST 24 21431100 ps
T56 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.898254242 Jan 10 01:00:15 PM PST 24 Jan 10 01:16:20 PM PST 24 3003585300 ps
T98 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1048457724 Jan 10 01:00:45 PM PST 24 Jan 10 01:02:36 PM PST 24 30469900 ps
T164 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.974005448 Jan 10 12:59:55 PM PST 24 Jan 10 01:01:57 PM PST 24 57280500 ps
T134 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3076594742 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:59 PM PST 24 22001500 ps
T40 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.392586064 Jan 10 01:00:14 PM PST 24 Jan 10 01:02:32 PM PST 24 28171900 ps
T128 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1212826463 Jan 10 01:00:23 PM PST 24 Jan 10 01:02:43 PM PST 24 223267400 ps
T133 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.596670015 Jan 10 01:00:46 PM PST 24 Jan 10 01:02:36 PM PST 24 78976600 ps
T92 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3694650668 Jan 10 01:00:20 PM PST 24 Jan 10 01:02:15 PM PST 24 90513000 ps
T99 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2209903132 Jan 10 01:00:31 PM PST 24 Jan 10 01:02:05 PM PST 24 25580700 ps
T61 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3304005237 Jan 10 01:00:44 PM PST 24 Jan 10 01:02:21 PM PST 24 133574700 ps
T107 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1062909425 Jan 10 01:00:35 PM PST 24 Jan 10 01:02:04 PM PST 24 57357100 ps
T165 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3861147747 Jan 10 01:00:06 PM PST 24 Jan 10 01:03:02 PM PST 24 82414800 ps
T166 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3617122758 Jan 10 01:00:04 PM PST 24 Jan 10 01:02:03 PM PST 24 158184800 ps
T167 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3897638723 Jan 10 12:59:59 PM PST 24 Jan 10 01:02:25 PM PST 24 2327608700 ps
T117 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2412847754 Jan 10 01:00:31 PM PST 24 Jan 10 01:02:04 PM PST 24 14165000 ps
T62 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1792341459 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:03 PM PST 24 49657900 ps
T168 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1356236355 Jan 10 01:00:02 PM PST 24 Jan 10 01:02:39 PM PST 24 319033400 ps
T169 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3791412489 Jan 10 01:00:03 PM PST 24 Jan 10 01:01:57 PM PST 24 21312000 ps
T45 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.353436133 Jan 10 01:00:15 PM PST 24 Jan 10 01:02:05 PM PST 24 100986800 ps
T170 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.434991570 Jan 10 12:59:54 PM PST 24 Jan 10 01:01:37 PM PST 24 96630500 ps
T46 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.473645238 Jan 10 01:00:01 PM PST 24 Jan 10 01:02:32 PM PST 24 265094000 ps
T171 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1783178205 Jan 10 01:00:23 PM PST 24 Jan 10 01:02:04 PM PST 24 19217200 ps
T68 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4237873251 Jan 10 01:00:03 PM PST 24 Jan 10 01:02:20 PM PST 24 824782900 ps
T120 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2844043798 Jan 10 01:00:40 PM PST 24 Jan 10 01:02:14 PM PST 24 48494000 ps
T47 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1648453427 Jan 10 01:00:01 PM PST 24 Jan 10 01:02:05 PM PST 24 52212800 ps
T172 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1534478610 Jan 10 01:00:19 PM PST 24 Jan 10 01:01:57 PM PST 24 61400400 ps
T173 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4162957711 Jan 10 01:00:28 PM PST 24 Jan 10 01:02:00 PM PST 24 28873900 ps
T84 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3296285581 Jan 10 01:00:02 PM PST 24 Jan 10 01:07:52 PM PST 24 3183324900 ps
T71 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.414874216 Jan 10 01:00:17 PM PST 24 Jan 10 01:16:34 PM PST 24 1155503600 ps
T79 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4287504031 Jan 10 01:00:17 PM PST 24 Jan 10 01:16:35 PM PST 24 376284500 ps
T127 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2908386946 Jan 10 12:59:57 PM PST 24 Jan 10 01:01:52 PM PST 24 29587200 ps
T174 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.476031199 Jan 10 01:00:11 PM PST 24 Jan 10 01:09:07 PM PST 24 322739400 ps
T175 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2972464735 Jan 10 01:00:08 PM PST 24 Jan 10 01:02:06 PM PST 24 102996100 ps
T176 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1520551644 Jan 10 01:00:03 PM PST 24 Jan 10 01:02:05 PM PST 24 642243000 ps
T49 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1952379873 Jan 10 01:00:19 PM PST 24 Jan 10 01:01:57 PM PST 24 34795200 ps
T109 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1002280155 Jan 10 01:00:27 PM PST 24 Jan 10 01:02:06 PM PST 24 66921000 ps
T123 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1029136336 Jan 10 12:59:51 PM PST 24 Jan 10 01:01:37 PM PST 24 28845700 ps
T177 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3996759944 Jan 10 01:00:19 PM PST 24 Jan 10 01:01:56 PM PST 24 12924600 ps
T126 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3181525630 Jan 10 01:01:04 PM PST 24 Jan 10 01:02:35 PM PST 24 16551300 ps
T178 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.570450526 Jan 10 01:00:40 PM PST 24 Jan 10 01:02:15 PM PST 24 35106800 ps
T179 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2818083945 Jan 10 01:00:19 PM PST 24 Jan 10 01:01:57 PM PST 24 31918200 ps
T131 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1866591792 Jan 10 01:00:08 PM PST 24 Jan 10 01:01:54 PM PST 24 51029500 ps
T122 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1113660357 Jan 10 01:00:13 PM PST 24 Jan 10 01:02:43 PM PST 24 30939900 ps
T180 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4033420212 Jan 10 01:00:19 PM PST 24 Jan 10 01:02:15 PM PST 24 65951700 ps
T112 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3089181432 Jan 10 01:00:27 PM PST 24 Jan 10 01:02:10 PM PST 24 53564300 ps
T72 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2623766665 Jan 10 01:00:43 PM PST 24 Jan 10 01:02:21 PM PST 24 119440600 ps
T181 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4022902253 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:04 PM PST 24 69340700 ps
T182 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1791190168 Jan 10 01:00:23 PM PST 24 Jan 10 01:02:11 PM PST 24 17991200 ps
T73 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2595447343 Jan 10 01:00:20 PM PST 24 Jan 10 01:02:21 PM PST 24 234658300 ps
T118 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4275854965 Jan 10 01:00:08 PM PST 24 Jan 10 01:02:12 PM PST 24 54781300 ps
T183 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3586349285 Jan 10 01:00:23 PM PST 24 Jan 10 01:02:20 PM PST 24 52709900 ps
T74 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2611820192 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:02 PM PST 24 23444700 ps
T124 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1305236058 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:48 PM PST 24 47931300 ps
T184 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.734515190 Jan 10 01:00:19 PM PST 24 Jan 10 01:02:44 PM PST 24 150536300 ps
T121 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2310405992 Jan 10 01:00:48 PM PST 24 Jan 10 01:02:27 PM PST 24 62702200 ps
T185 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1115291493 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:47 PM PST 24 104253800 ps
T186 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.593113646 Jan 10 12:59:57 PM PST 24 Jan 10 01:02:46 PM PST 24 3278922100 ps
T187 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3857378066 Jan 10 01:01:13 PM PST 24 Jan 10 01:02:54 PM PST 24 21327400 ps
T188 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3894816197 Jan 10 01:00:07 PM PST 24 Jan 10 01:01:49 PM PST 24 19010100 ps
T189 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4019834166 Jan 10 01:00:05 PM PST 24 Jan 10 01:02:02 PM PST 24 135534500 ps
T78 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2264205076 Jan 10 01:00:14 PM PST 24 Jan 10 01:17:07 PM PST 24 1353515100 ps
T190 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1904196833 Jan 10 01:00:24 PM PST 24 Jan 10 01:02:25 PM PST 24 41692200 ps
T191 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2202245528 Jan 10 01:01:05 PM PST 24 Jan 10 01:02:34 PM PST 24 27343600 ps
T192 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1256630091 Jan 10 12:59:59 PM PST 24 Jan 10 01:02:23 PM PST 24 7880612000 ps
T193 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1668153883 Jan 10 01:00:06 PM PST 24 Jan 10 01:14:22 PM PST 24 1866998900 ps
T194 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.959277764 Jan 10 01:00:09 PM PST 24 Jan 10 01:02:09 PM PST 24 18357300 ps
T110 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2026892894 Jan 10 01:00:52 PM PST 24 Jan 10 01:02:38 PM PST 24 64550300 ps
T81 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.614091211 Jan 10 01:00:06 PM PST 24 Jan 10 01:08:06 PM PST 24 1430216300 ps
T195 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2857345895 Jan 10 01:00:28 PM PST 24 Jan 10 01:02:07 PM PST 24 25609500 ps
T132 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2336807011 Jan 10 01:00:13 PM PST 24 Jan 10 01:02:16 PM PST 24 41126400 ps
T101 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2043589137 Jan 10 01:00:12 PM PST 24 Jan 10 01:02:09 PM PST 24 35357000 ps
T196 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3442922303 Jan 10 01:00:12 PM PST 24 Jan 10 01:01:51 PM PST 24 20908400 ps
T116 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.600624505 Jan 10 01:00:19 PM PST 24 Jan 10 01:02:23 PM PST 24 266251100 ps
T119 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1090778756 Jan 10 01:00:41 PM PST 24 Jan 10 01:02:22 PM PST 24 106758700 ps
T197 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3804281156 Jan 10 01:00:20 PM PST 24 Jan 10 01:02:10 PM PST 24 48825300 ps
T198 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3030249412 Jan 10 01:00:19 PM PST 24 Jan 10 01:01:57 PM PST 24 253188300 ps
T199 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1318112476 Jan 10 01:00:17 PM PST 24 Jan 10 01:02:16 PM PST 24 70958300 ps
T200 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3349754789 Jan 10 01:00:16 PM PST 24 Jan 10 01:02:04 PM PST 24 86619400 ps
T201 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3215752488 Jan 10 01:00:10 PM PST 24 Jan 10 01:01:51 PM PST 24 17175000 ps
T130 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2051809473 Jan 10 01:01:04 PM PST 24 Jan 10 01:02:35 PM PST 24 18505500 ps
T202 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4280422420 Jan 10 01:00:07 PM PST 24 Jan 10 01:02:11 PM PST 24 310052200 ps
T129 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3513821715 Jan 10 01:01:02 PM PST 24 Jan 10 01:02:42 PM PST 24 25362400 ps
T203 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4156209152 Jan 10 01:00:09 PM PST 24 Jan 10 01:02:06 PM PST 24 617560800 ps
T75 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1190175014 Jan 10 01:00:17 PM PST 24 Jan 10 01:02:20 PM PST 24 103867000 ps
T204 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1452176803 Jan 10 01:00:40 PM PST 24 Jan 10 01:02:15 PM PST 24 17387200 ps
T205 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2657629030 Jan 10 01:00:09 PM PST 24 Jan 10 01:02:19 PM PST 24 153787300 ps
T206 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1125941123 Jan 10 12:59:55 PM PST 24 Jan 10 01:01:48 PM PST 24 194217200 ps
T76 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1740145439 Jan 10 01:00:48 PM PST 24 Jan 10 01:02:24 PM PST 24 27523100 ps
T207 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2062586188 Jan 10 01:00:10 PM PST 24 Jan 10 01:02:20 PM PST 24 93429300 ps
T208 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2043972105 Jan 10 01:00:15 PM PST 24 Jan 10 01:02:15 PM PST 24 37179800 ps
T125 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3642348298 Jan 10 01:00:19 PM PST 24 Jan 10 01:02:18 PM PST 24 30997000 ps
T209 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.24350839 Jan 10 12:59:59 PM PST 24 Jan 10 01:01:57 PM PST 24 13504000 ps
T210 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3071906535 Jan 10 01:00:11 PM PST 24 Jan 10 01:02:13 PM PST 24 421519900 ps
T211 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2358412605 Jan 10 01:00:00 PM PST 24 Jan 10 01:01:58 PM PST 24 42747000 ps

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.535882417
Short name T2
Test name
Test status
Simulation time 46224600 ps
CPU time 17.62 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:01:53 PM PST 24
Peak memory 262968 kb
Host smart-362fd2a6-1c02-4bf3-9087-48096f246e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535882417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.535882417
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2279744009
Short name T14
Test name
Test status
Simulation time 8234077400 ps
CPU time 468.01 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:09:35 PM PST 24
Peak memory 262972 kb
Host smart-12648ab6-83ab-4e79-be2c-f8b09f5ae6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279744009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.2279744009
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2213791585
Short name T12
Test name
Test status
Simulation time 49660000 ps
CPU time 18.61 seconds
Started Jan 10 01:00:07 PM PST 24
Finished Jan 10 01:01:55 PM PST 24
Peak memory 262964 kb
Host smart-1b39da88-f5f9-4122-b007-8ce6b74f7b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213791585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
213791585
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.683871529
Short name T7
Test name
Test status
Simulation time 16001600 ps
CPU time 13.14 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:55 PM PST 24
Peak memory 260948 kb
Host smart-29af6bcc-f5c1-44c5-8338-7a0045782e47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683871529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.683871529
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2685229894
Short name T5
Test name
Test status
Simulation time 343906300 ps
CPU time 891.21 seconds
Started Jan 10 01:00:10 PM PST 24
Finished Jan 10 01:17:00 PM PST 24
Peak memory 262960 kb
Host smart-ae4d75a0-4a9e-4103-b6cd-b10789895ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685229894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2685229894
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4131475000
Short name T21
Test name
Test status
Simulation time 25908800 ps
CPU time 13.34 seconds
Started Jan 10 01:00:02 PM PST 24
Finished Jan 10 01:01:43 PM PST 24
Peak memory 262320 kb
Host smart-48a744ff-6092-4b17-815d-a763268d2f82
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131475000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.4131475000
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1677136719
Short name T9
Test name
Test status
Simulation time 93161400 ps
CPU time 13.41 seconds
Started Jan 10 01:00:10 PM PST 24
Finished Jan 10 01:02:22 PM PST 24
Peak memory 260848 kb
Host smart-f646d626-5e8e-47c1-9c5c-d7b0a510ccf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677136719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.1
677136719
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2325519797
Short name T24
Test name
Test status
Simulation time 57306700 ps
CPU time 18.3 seconds
Started Jan 10 12:59:56 PM PST 24
Finished Jan 10 01:01:45 PM PST 24
Peak memory 263008 kb
Host smart-8eda3f7d-66af-4ea9-8a8c-9e1527c37383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325519797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.2
325519797
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3203417537
Short name T25
Test name
Test status
Simulation time 195949900 ps
CPU time 18.38 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:50 PM PST 24
Peak memory 262900 kb
Host smart-cb9bfda7-d7c9-43a6-a97f-d644144eb2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203417537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3
203417537
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3146976785
Short name T23
Test name
Test status
Simulation time 38680200 ps
CPU time 16.45 seconds
Started Jan 10 01:00:20 PM PST 24
Finished Jan 10 01:02:25 PM PST 24
Peak memory 262972 kb
Host smart-50738991-a211-4dc7-a832-1ab66ebe71b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146976785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3
146976785
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2517625786
Short name T90
Test name
Test status
Simulation time 14922700 ps
CPU time 13.22 seconds
Started Jan 10 01:00:05 PM PST 24
Finished Jan 10 01:02:07 PM PST 24
Peak memory 260064 kb
Host smart-e41445f6-ef3c-4b06-825f-5ab35e48a6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517625786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
517625786
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.451411765
Short name T102
Test name
Test status
Simulation time 45868800 ps
CPU time 13.16 seconds
Started Jan 10 01:00:56 PM PST 24
Finished Jan 10 01:02:41 PM PST 24
Peak memory 261044 kb
Host smart-f1ab8ef7-0ed2-4e6c-81d0-c87039ac5a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451411765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.451411765
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3858924109
Short name T82
Test name
Test status
Simulation time 354108300 ps
CPU time 871.75 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:16:18 PM PST 24
Peak memory 262900 kb
Host smart-109352a1-3c6e-4c63-a490-94d39aa61f02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858924109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.3858924109
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1363542477
Short name T20
Test name
Test status
Simulation time 47976900 ps
CPU time 13.02 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:01:47 PM PST 24
Peak memory 260080 kb
Host smart-12deadcd-5af1-426b-98d4-329ca57ca309
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363542477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1363542477
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2329024860
Short name T43
Test name
Test status
Simulation time 28144400 ps
CPU time 13.05 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:02:25 PM PST 24
Peak memory 260964 kb
Host smart-20e82bdd-7342-4b16-a325-54a8a66bee32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329024860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2329024860
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3434538704
Short name T17
Test name
Test status
Simulation time 371578700 ps
CPU time 15.94 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:02:46 PM PST 24
Peak memory 263020 kb
Host smart-1030e7e4-5839-4a43-8cb6-280e69177d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434538704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3434538704
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1648453427
Short name T47
Test name
Test status
Simulation time 52212800 ps
CPU time 18.9 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 262904 kb
Host smart-874d132a-3449-4f04-8b03-f469018cc3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648453427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
648453427
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2611820192
Short name T74
Test name
Test status
Simulation time 23444700 ps
CPU time 16.22 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:02 PM PST 24
Peak memory 260688 kb
Host smart-e35ccd0b-50d7-4838-b8ca-0ae6a3bc7c70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611820192 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2611820192
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1048457724
Short name T98
Test name
Test status
Simulation time 30469900 ps
CPU time 13.18 seconds
Started Jan 10 01:00:45 PM PST 24
Finished Jan 10 01:02:36 PM PST 24
Peak memory 261172 kb
Host smart-85e59305-b492-4beb-9170-e1ac28e681a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048457724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
1048457724
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3668556536
Short name T111
Test name
Test status
Simulation time 53127600 ps
CPU time 13.18 seconds
Started Jan 10 01:00:50 PM PST 24
Finished Jan 10 01:02:27 PM PST 24
Peak memory 261020 kb
Host smart-0488eab1-854a-44ca-82f0-4dbe308eb9e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668556536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.3668556536
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3181525630
Short name T126
Test name
Test status
Simulation time 16551300 ps
CPU time 13.12 seconds
Started Jan 10 01:01:04 PM PST 24
Finished Jan 10 01:02:35 PM PST 24
Peak memory 260780 kb
Host smart-e85ed132-4318-41b2-be26-de45f39e3d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181525630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
3181525630
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4275854965
Short name T118
Test name
Test status
Simulation time 54781300 ps
CPU time 18.52 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:02:12 PM PST 24
Peak memory 262968 kb
Host smart-6eaaa931-8e2a-41c0-b3ee-1bd363f5282c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275854965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.4
275854965
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1255874975
Short name T91
Test name
Test status
Simulation time 15047800 ps
CPU time 13.24 seconds
Started Jan 10 01:00:31 PM PST 24
Finished Jan 10 01:02:02 PM PST 24
Peak memory 261096 kb
Host smart-1d5764d6-3050-4713-9138-cd31e5d0655a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255874975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
1255874975
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2229217610
Short name T104
Test name
Test status
Simulation time 68593800 ps
CPU time 13.38 seconds
Started Jan 10 01:00:32 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 260952 kb
Host smart-aea18ff0-9a84-4fe4-a679-ee3ad84a7f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229217610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
2229217610
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4287504031
Short name T79
Test name
Test status
Simulation time 376284500 ps
CPU time 886.51 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:16:35 PM PST 24
Peak memory 258840 kb
Host smart-10296b0b-42cc-4e87-849a-7e6b78acb93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287504031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.4287504031
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3735305409
Short name T80
Test name
Test status
Simulation time 1405454000 ps
CPU time 889.89 seconds
Started Jan 10 01:00:44 PM PST 24
Finished Jan 10 01:16:49 PM PST 24
Peak memory 263012 kb
Host smart-39de0300-b760-42cf-ae7e-d63c15fa735d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735305409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.3735305409
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3094828630
Short name T103
Test name
Test status
Simulation time 27542200 ps
CPU time 13.17 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:01:48 PM PST 24
Peak memory 260000 kb
Host smart-4b40dd75-fc4a-415d-ab7b-3e49fc734c7d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094828630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3094828630
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1282068783
Short name T28
Test name
Test status
Simulation time 95946700 ps
CPU time 19.15 seconds
Started Jan 10 01:00:43 PM PST 24
Finished Jan 10 01:02:12 PM PST 24
Peak memory 262856 kb
Host smart-49ff8aff-229d-4981-9a89-124af2b21bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282068783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
1282068783
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.15422125
Short name T36
Test name
Test status
Simulation time 17680200 ps
CPU time 13.53 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:01:47 PM PST 24
Peak memory 262528 kb
Host smart-620fbf3c-0a6d-44ed-8f61-b93b643e5b39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15422125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_mem_partial_access.15422125
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1002280155
Short name T109
Test name
Test status
Simulation time 66921000 ps
CPU time 14.99 seconds
Started Jan 10 01:00:27 PM PST 24
Finished Jan 10 01:02:06 PM PST 24
Peak memory 262900 kb
Host smart-7090a68a-12e1-462c-bdde-de7507ef7bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002280155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1002280155
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1113660357
Short name T122
Test name
Test status
Simulation time 30939900 ps
CPU time 13.23 seconds
Started Jan 10 01:00:13 PM PST 24
Finished Jan 10 01:02:43 PM PST 24
Peak memory 260008 kb
Host smart-f948def1-3b41-4a00-a6c0-e1d9314285bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113660357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
1113660357
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3707345103
Short name T105
Test name
Test status
Simulation time 29893700 ps
CPU time 13.28 seconds
Started Jan 10 01:00:36 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 261028 kb
Host smart-e55fd845-8d56-4d11-87eb-3e652202737c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707345103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3707345103
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.698102827
Short name T54
Test name
Test status
Simulation time 157769600 ps
CPU time 15.23 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 271152 kb
Host smart-8df4784d-9475-43d7-902e-029e922405f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698102827 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.698102827
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3642348298
Short name T125
Test name
Test status
Simulation time 30997000 ps
CPU time 13.25 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:02:18 PM PST 24
Peak memory 260852 kb
Host smart-4b13d8fa-a44e-4e17-94e3-060a86778598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642348298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
3642348298
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1952379873
Short name T49
Test name
Test status
Simulation time 34795200 ps
CPU time 15.94 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 262980 kb
Host smart-4517253d-81f1-49e6-b5f7-d59a900bdabb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952379873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1952379873
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3942568623
Short name T30
Test name
Test status
Simulation time 36082000 ps
CPU time 16.55 seconds
Started Jan 10 01:00:24 PM PST 24
Finished Jan 10 01:02:38 PM PST 24
Peak memory 262952 kb
Host smart-e63641e9-691a-4718-8b50-098a656b236d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942568623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3942568623
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.474093514
Short name T114
Test name
Test status
Simulation time 17904300 ps
CPU time 13.24 seconds
Started Jan 10 01:00:31 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 261108 kb
Host smart-e8c2ca13-639e-4fee-a9bf-8d2baf2c4919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474093514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.474093514
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.614091211
Short name T81
Test name
Test status
Simulation time 1430216300 ps
CPU time 379.37 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:08:06 PM PST 24
Peak memory 262900 kb
Host smart-b7056e32-4d17-46e9-996e-4a6ed2e21ced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614091211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.614091211
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.812029932
Short name T53
Test name
Test status
Simulation time 1353781100 ps
CPU time 885.69 seconds
Started Jan 10 01:00:21 PM PST 24
Finished Jan 10 01:16:35 PM PST 24
Peak memory 258796 kb
Host smart-a05b95be-e67a-4431-9913-c58dd9ca5d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812029932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_tl_intg_err.812029932
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3897638723
Short name T167
Test name
Test status
Simulation time 2327608700 ps
CPU time 53.97 seconds
Started Jan 10 12:59:59 PM PST 24
Finished Jan 10 01:02:25 PM PST 24
Peak memory 258756 kb
Host smart-eeb5d342-c39a-48a9-a272-c9decfbce912
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897638723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.3897638723
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1256630091
Short name T192
Test name
Test status
Simulation time 7880612000 ps
CPU time 47.53 seconds
Started Jan 10 12:59:59 PM PST 24
Finished Jan 10 01:02:23 PM PST 24
Peak memory 258844 kb
Host smart-6e61737a-2551-432f-9588-7fa8cec86248
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256630091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.1256630091
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1365775346
Short name T67
Test name
Test status
Simulation time 43917300 ps
CPU time 37.8 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:59 PM PST 24
Peak memory 258816 kb
Host smart-7a358a00-8e5d-4efc-bfd4-9085dcf46c27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365775346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1365775346
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2998528242
Short name T37
Test name
Test status
Simulation time 179269700 ps
CPU time 14.59 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:01:59 PM PST 24
Peak memory 258756 kb
Host smart-143a3ff4-bc38-406d-8ef0-68f5caf6efc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998528242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.2998528242
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1029136336
Short name T123
Test name
Test status
Simulation time 28845700 ps
CPU time 13.1 seconds
Started Jan 10 12:59:51 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 261172 kb
Host smart-adf19878-dce1-4680-b673-79c34c4c2885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029136336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
029136336
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.348152035
Short name T1
Test name
Test status
Simulation time 17445900 ps
CPU time 13.24 seconds
Started Jan 10 12:59:53 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 261968 kb
Host smart-85a41f06-42d7-404e-bfcf-1c426d504e3e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348152035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.348152035
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4090891858
Short name T59
Test name
Test status
Simulation time 16000000 ps
CPU time 13.06 seconds
Started Jan 10 01:00:12 PM PST 24
Finished Jan 10 01:02:36 PM PST 24
Peak memory 260016 kb
Host smart-97b9fc6b-a3c0-4f68-a601-8fef158d770a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090891858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.4090891858
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3073672173
Short name T143
Test name
Test status
Simulation time 159391200 ps
CPU time 33.62 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:02:08 PM PST 24
Peak memory 258804 kb
Host smart-d6fd8c2d-38f5-4335-bd6e-8cf7f22303b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073672173 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3073672173
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.434991570
Short name T170
Test name
Test status
Simulation time 96630500 ps
CPU time 13.21 seconds
Started Jan 10 12:59:54 PM PST 24
Finished Jan 10 01:01:37 PM PST 24
Peak memory 258708 kb
Host smart-b8749ac1-09ec-4ac7-984b-9a88b68a8cb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434991570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.434991570
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2733002028
Short name T64
Test name
Test status
Simulation time 23133100 ps
CPU time 15.45 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:49 PM PST 24
Peak memory 258700 kb
Host smart-a7ad4ab8-44d3-460b-ab44-47d11c04a8b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733002028 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2733002028
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1520551644
Short name T176
Test name
Test status
Simulation time 642243000 ps
CPU time 35.6 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 258784 kb
Host smart-7340b642-890b-40eb-8461-4ba806abf33b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520551644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1520551644
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2455327408
Short name T38
Test name
Test status
Simulation time 8385404600 ps
CPU time 68.27 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:02:53 PM PST 24
Peak memory 261620 kb
Host smart-f40d31d9-19d7-4126-9212-605bdcbf141b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455327408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.2455327408
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1924654667
Short name T69
Test name
Test status
Simulation time 309991100 ps
CPU time 45.54 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:02:50 PM PST 24
Peak memory 258848 kb
Host smart-543c6433-464f-4f5f-9045-f071c21d451f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924654667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.1924654667
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3076594742
Short name T134
Test name
Test status
Simulation time 22001500 ps
CPU time 17.38 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:59 PM PST 24
Peak memory 274388 kb
Host smart-2e0135c6-58ed-41fa-a5f7-e95493645c38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076594742 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3076594742
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1356236355
Short name T168
Test name
Test status
Simulation time 319033400 ps
CPU time 16.2 seconds
Started Jan 10 01:00:02 PM PST 24
Finished Jan 10 01:02:39 PM PST 24
Peak memory 258748 kb
Host smart-bf94bbc0-c9ec-474a-a6b4-f80e4f20e285
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356236355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1356236355
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2908386946
Short name T127
Test name
Test status
Simulation time 29587200 ps
CPU time 13.12 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:52 PM PST 24
Peak memory 260816 kb
Host smart-c3763842-c23e-4aa7-b4d4-f505e806a260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908386946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2
908386946
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3009325825
Short name T39
Test name
Test status
Simulation time 17879900 ps
CPU time 13.37 seconds
Started Jan 10 01:00:02 PM PST 24
Finished Jan 10 01:02:27 PM PST 24
Peak memory 262852 kb
Host smart-2ad33bdd-3424-4980-b1e1-79a5e0971467
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009325825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.3009325825
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3617122758
Short name T166
Test name
Test status
Simulation time 158184800 ps
CPU time 29.15 seconds
Started Jan 10 01:00:04 PM PST 24
Finished Jan 10 01:02:03 PM PST 24
Peak memory 261396 kb
Host smart-cca089a0-cd59-4549-8e33-d20bdf8004e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617122758 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3617122758
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3376897910
Short name T156
Test name
Test status
Simulation time 40193800 ps
CPU time 13.06 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:48 PM PST 24
Peak memory 258772 kb
Host smart-ae2229c8-c58b-4053-9a97-59756f710532
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376897910 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.3376897910
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.24350839
Short name T209
Test name
Test status
Simulation time 13504000 ps
CPU time 15.33 seconds
Started Jan 10 12:59:59 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 258776 kb
Host smart-95ac1a55-c9c1-4b9b-85bf-2fcc5e3068b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350839 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.24350839
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.473645238
Short name T46
Test name
Test status
Simulation time 265094000 ps
CPU time 18.16 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:02:32 PM PST 24
Peak memory 262988 kb
Host smart-e11f1df0-bf9e-4245-b790-8b732291437d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473645238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.473645238
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3296285581
Short name T84
Test name
Test status
Simulation time 3183324900 ps
CPU time 382.52 seconds
Started Jan 10 01:00:02 PM PST 24
Finished Jan 10 01:07:52 PM PST 24
Peak memory 262992 kb
Host smart-4aa2eb19-8abb-41a0-9b5a-e12c97cd0997
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296285581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3296285581
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.699741005
Short name T27
Test name
Test status
Simulation time 44165100 ps
CPU time 17.61 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:02:16 PM PST 24
Peak memory 271392 kb
Host smart-f6f0705a-43ef-4f82-bd32-d89353a02843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699741005 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.699741005
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2818083945
Short name T179
Test name
Test status
Simulation time 31918200 ps
CPU time 15.97 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 258840 kb
Host smart-a4d6d491-c880-4154-aed6-1a1f8def1ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818083945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2818083945
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1731613515
Short name T8
Test name
Test status
Simulation time 33974600 ps
CPU time 13.21 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:22 PM PST 24
Peak memory 260052 kb
Host smart-b41069af-07be-4fb8-b721-5cff77bb86a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731613515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1731613515
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3349754789
Short name T200
Test name
Test status
Simulation time 86619400 ps
CPU time 17.18 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 258816 kb
Host smart-71abe50c-1d63-4ca2-ba8b-0c0bef4f209f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349754789 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3349754789
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1302619445
Short name T138
Test name
Test status
Simulation time 83869600 ps
CPU time 15.27 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:46 PM PST 24
Peak memory 258732 kb
Host smart-4bad4987-95da-404a-a822-a4a48a632bc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302619445 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1302619445
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.591010569
Short name T158
Test name
Test status
Simulation time 14859100 ps
CPU time 12.97 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:02:12 PM PST 24
Peak memory 258716 kb
Host smart-e728bcb9-b205-4560-b2ac-638a0191c205
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591010569 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.591010569
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.820264016
Short name T15
Test name
Test status
Simulation time 277973800 ps
CPU time 16.7 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:02:26 PM PST 24
Peak memory 258816 kb
Host smart-90aa3577-8150-4d81-8816-a1667185c4f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820264016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.820264016
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2844043798
Short name T120
Test name
Test status
Simulation time 48494000 ps
CPU time 13.04 seconds
Started Jan 10 01:00:40 PM PST 24
Finished Jan 10 01:02:14 PM PST 24
Peak memory 261096 kb
Host smart-6c88987c-97ad-45da-af89-1e456912b52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844043798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
2844043798
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.4144574982
Short name T4
Test name
Test status
Simulation time 492229300 ps
CPU time 33.36 seconds
Started Jan 10 01:00:13 PM PST 24
Finished Jan 10 01:02:20 PM PST 24
Peak memory 258872 kb
Host smart-710ab972-4ede-4259-b833-0e5a7161f06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144574982 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.4144574982
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2780097083
Short name T139
Test name
Test status
Simulation time 60707200 ps
CPU time 15.27 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:01:53 PM PST 24
Peak memory 258824 kb
Host smart-54f7ff6e-4164-430b-9bb5-c9716604a44c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780097083 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2780097083
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1952498383
Short name T136
Test name
Test status
Simulation time 29393400 ps
CPU time 15.53 seconds
Started Jan 10 01:00:47 PM PST 24
Finished Jan 10 01:02:11 PM PST 24
Peak memory 258592 kb
Host smart-7a5ddcc5-1a5a-4023-9e82-c40891f95cc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952498383 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1952498383
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1866591792
Short name T131
Test name
Test status
Simulation time 51029500 ps
CPU time 14.12 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:54 PM PST 24
Peak memory 263048 kb
Host smart-f1ffa300-fb1c-4171-8012-dc91db76afa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866591792 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1866591792
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3304005237
Short name T61
Test name
Test status
Simulation time 133574700 ps
CPU time 16.81 seconds
Started Jan 10 01:00:44 PM PST 24
Finished Jan 10 01:02:21 PM PST 24
Peak memory 258904 kb
Host smart-5e8c812d-f716-4ed0-acf7-696549c4915f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304005237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3304005237
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4022902253
Short name T181
Test name
Test status
Simulation time 69340700 ps
CPU time 17.32 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 260996 kb
Host smart-c7e39493-dd55-4ff6-8a2a-134331a33885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022902253 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.4022902253
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.959277764
Short name T194
Test name
Test status
Simulation time 18357300 ps
CPU time 15.2 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:02:09 PM PST 24
Peak memory 258668 kb
Host smart-a75a67e4-2f65-4f09-840c-e7a40a0c2fe2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959277764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.959277764
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3905998577
Short name T163
Test name
Test status
Simulation time 24885900 ps
CPU time 15.32 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:01:53 PM PST 24
Peak memory 258828 kb
Host smart-a2e90c5d-5ab5-4e7c-b966-1dceeafce22c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905998577 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3905998577
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3030249412
Short name T198
Test name
Test status
Simulation time 253188300 ps
CPU time 15.83 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 271152 kb
Host smart-f911a9ae-9ec3-409a-b2c7-3d5396f7c13a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030249412 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.3030249412
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.785546796
Short name T151
Test name
Test status
Simulation time 744838100 ps
CPU time 17.32 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:01:55 PM PST 24
Peak memory 258888 kb
Host smart-7cf567cf-278b-4850-8c77-21eb0c011855
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785546796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.785546796
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.922095281
Short name T147
Test name
Test status
Simulation time 91134300 ps
CPU time 18.06 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:02:27 PM PST 24
Peak memory 260416 kb
Host smart-ece1c07a-d5ea-4fc5-ab06-5b3b86b8a380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922095281 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.922095281
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3442922303
Short name T196
Test name
Test status
Simulation time 20908400 ps
CPU time 15.25 seconds
Started Jan 10 01:00:12 PM PST 24
Finished Jan 10 01:01:51 PM PST 24
Peak memory 258784 kb
Host smart-9f180f6e-f227-40f3-b2af-cb9baad987cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442922303 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3442922303
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3215752488
Short name T201
Test name
Test status
Simulation time 17175000 ps
CPU time 15.48 seconds
Started Jan 10 01:00:10 PM PST 24
Finished Jan 10 01:01:51 PM PST 24
Peak memory 258824 kb
Host smart-24240d10-bab5-49d7-809b-fa9477753488
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215752488 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.3215752488
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.4105909413
Short name T22
Test name
Test status
Simulation time 37030300 ps
CPU time 16.72 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:02:45 PM PST 24
Peak memory 261720 kb
Host smart-39c0eaf0-ff90-4d6c-bcf9-1cbc7765a7e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105909413 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.4105909413
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1318112476
Short name T199
Test name
Test status
Simulation time 70958300 ps
CPU time 14.51 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:02:16 PM PST 24
Peak memory 258780 kb
Host smart-79905a5c-97ee-4840-8fea-0d7e7e468455
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318112476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1318112476
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2262961940
Short name T160
Test name
Test status
Simulation time 486993300 ps
CPU time 29.3 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:02:38 PM PST 24
Peak memory 258864 kb
Host smart-ec4342e3-3ac1-4b50-8576-b697c72e2038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262961940 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2262961940
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.907683244
Short name T135
Test name
Test status
Simulation time 11761000 ps
CPU time 12.89 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:02:06 PM PST 24
Peak memory 258748 kb
Host smart-fc8184c8-329c-41ea-ba54-6be70253046c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907683244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.907683244
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4238409752
Short name T65
Test name
Test status
Simulation time 11521100 ps
CPU time 15.26 seconds
Started Jan 10 01:00:12 PM PST 24
Finished Jan 10 01:02:02 PM PST 24
Peak memory 258776 kb
Host smart-41030248-a17e-4b9e-9d56-7f949a430e5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238409752 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.4238409752
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.414874216
Short name T71
Test name
Test status
Simulation time 1155503600 ps
CPU time 885.35 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:16:34 PM PST 24
Peak memory 262996 kb
Host smart-5327f4f6-f8b7-4c2b-8b60-f5e962df5204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414874216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.414874216
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3804281156
Short name T197
Test name
Test status
Simulation time 48825300 ps
CPU time 16.38 seconds
Started Jan 10 01:00:20 PM PST 24
Finished Jan 10 01:02:10 PM PST 24
Peak memory 261648 kb
Host smart-23011721-5c1c-49e6-97ca-94b75cc293ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804281156 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3804281156
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2761042977
Short name T86
Test name
Test status
Simulation time 673972800 ps
CPU time 16.84 seconds
Started Jan 10 01:00:24 PM PST 24
Finished Jan 10 01:02:40 PM PST 24
Peak memory 258916 kb
Host smart-8f9aa6f8-73ba-4568-801f-864726e87a6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761042977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2761042977
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.791758740
Short name T60
Test name
Test status
Simulation time 14921300 ps
CPU time 13.19 seconds
Started Jan 10 01:00:23 PM PST 24
Finished Jan 10 01:02:17 PM PST 24
Peak memory 260832 kb
Host smart-ec1bbf1a-32a3-4ff7-b051-16a322e8bde3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791758740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.791758740
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.291471038
Short name T35
Test name
Test status
Simulation time 448664900 ps
CPU time 34.06 seconds
Started Jan 10 01:00:29 PM PST 24
Finished Jan 10 01:03:06 PM PST 24
Peak memory 258916 kb
Host smart-a6b054b8-a51b-4db8-976a-5e98a9197b4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291471038 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.291471038
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1458573128
Short name T42
Test name
Test status
Simulation time 77976900 ps
CPU time 13 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:01:59 PM PST 24
Peak memory 258632 kb
Host smart-b3b5d0d2-be6f-4113-b88a-408282be9fc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458573128 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.1458573128
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4270389299
Short name T162
Test name
Test status
Simulation time 11476800 ps
CPU time 12.91 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:01:51 PM PST 24
Peak memory 258808 kb
Host smart-0caceb4a-4601-4dc1-b5d3-1058c1a4fb1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270389299 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.4270389299
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2043972105
Short name T208
Test name
Test status
Simulation time 37179800 ps
CPU time 16.24 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 262876 kb
Host smart-13fb058d-1341-403f-b28a-011b694ad085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043972105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2043972105
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.476031199
Short name T174
Test name
Test status
Simulation time 322739400 ps
CPU time 451 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:09:07 PM PST 24
Peak memory 258816 kb
Host smart-004295e4-c693-4575-9ad2-f86a9afa57aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476031199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.476031199
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1792341459
Short name T62
Test name
Test status
Simulation time 49657900 ps
CPU time 16.43 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:03 PM PST 24
Peak memory 271144 kb
Host smart-65d1c0f0-4b9e-4b07-83f4-4e1d2df84be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792341459 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1792341459
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3586349285
Short name T183
Test name
Test status
Simulation time 52709900 ps
CPU time 16.5 seconds
Started Jan 10 01:00:23 PM PST 24
Finished Jan 10 01:02:20 PM PST 24
Peak memory 258852 kb
Host smart-36d4bdc0-79c6-49bd-a56c-07fd4d38406f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586349285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.3586349285
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.648783720
Short name T106
Test name
Test status
Simulation time 28256400 ps
CPU time 13.14 seconds
Started Jan 10 01:00:22 PM PST 24
Finished Jan 10 01:02:06 PM PST 24
Peak memory 261124 kb
Host smart-3d4e0036-4354-49a8-83bf-d87755b3252c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648783720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.648783720
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1190175014
Short name T75
Test name
Test status
Simulation time 103867000 ps
CPU time 17.55 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:02:20 PM PST 24
Peak memory 258784 kb
Host smart-7f4d887a-2463-44ac-a5a4-ccef8d6c572e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190175014 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.1190175014
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1672083687
Short name T159
Test name
Test status
Simulation time 55154600 ps
CPU time 15.15 seconds
Started Jan 10 01:00:21 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 258768 kb
Host smart-6106e225-2b07-46b6-99fb-80dd4d5c645b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672083687 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1672083687
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1106455939
Short name T70
Test name
Test status
Simulation time 26313000 ps
CPU time 15.15 seconds
Started Jan 10 01:00:24 PM PST 24
Finished Jan 10 01:02:46 PM PST 24
Peak memory 258740 kb
Host smart-e6de0257-0669-4a3a-b6d9-5a768eb72ce0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106455939 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1106455939
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1115291493
Short name T185
Test name
Test status
Simulation time 104253800 ps
CPU time 19.37 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:47 PM PST 24
Peak memory 270780 kb
Host smart-dae47750-882c-4e9c-95ca-0ce509ca869a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115291493 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1115291493
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4033420212
Short name T180
Test name
Test status
Simulation time 65951700 ps
CPU time 13.82 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 258732 kb
Host smart-51da148f-3a0b-43cd-9570-dbbdb0a92854
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033420212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.4033420212
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3491474502
Short name T100
Test name
Test status
Simulation time 158536800 ps
CPU time 13.3 seconds
Started Jan 10 01:00:24 PM PST 24
Finished Jan 10 01:02:41 PM PST 24
Peak memory 261180 kb
Host smart-9be033a7-9a29-4124-b80f-7e568daa0b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491474502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3491474502
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3355330339
Short name T10
Test name
Test status
Simulation time 467825000 ps
CPU time 17.63 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:01:58 PM PST 24
Peak memory 258792 kb
Host smart-414b1c1e-b4d8-49bb-90b0-3dc691d792d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355330339 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3355330339
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4054469650
Short name T41
Test name
Test status
Simulation time 14036300 ps
CPU time 15.25 seconds
Started Jan 10 01:00:23 PM PST 24
Finished Jan 10 01:02:44 PM PST 24
Peak memory 258824 kb
Host smart-b2ba5e57-d7af-4373-a1dc-7d91281ed3ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054469650 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.4054469650
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1904196833
Short name T190
Test name
Test status
Simulation time 41692200 ps
CPU time 15.12 seconds
Started Jan 10 01:00:24 PM PST 24
Finished Jan 10 01:02:25 PM PST 24
Peak memory 258832 kb
Host smart-3f1cb731-8e70-4474-b669-bbc433db1578
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904196833 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1904196833
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.600624505
Short name T116
Test name
Test status
Simulation time 266251100 ps
CPU time 18.34 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:02:23 PM PST 24
Peak memory 262968 kb
Host smart-3800f8e8-2ed0-4497-a8ef-6ab4e339bcab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600624505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.600624505
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.898254242
Short name T56
Test name
Test status
Simulation time 3003585300 ps
CPU time 882.49 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:16:20 PM PST 24
Peak memory 258920 kb
Host smart-8734a743-f002-4e12-9117-db79e7c4e003
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898254242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.898254242
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1740145439
Short name T76
Test name
Test status
Simulation time 27523100 ps
CPU time 16.57 seconds
Started Jan 10 01:00:48 PM PST 24
Finished Jan 10 01:02:24 PM PST 24
Peak memory 261600 kb
Host smart-62b6b804-5fa5-428c-9c55-370e9793c103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740145439 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1740145439
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2539152569
Short name T32
Test name
Test status
Simulation time 49567700 ps
CPU time 16.89 seconds
Started Jan 10 01:00:26 PM PST 24
Finished Jan 10 01:02:10 PM PST 24
Peak memory 258820 kb
Host smart-ab756b05-a418-4ef5-a8aa-db99a2c67902
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539152569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.2539152569
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3694650668
Short name T92
Test name
Test status
Simulation time 90513000 ps
CPU time 13.3 seconds
Started Jan 10 01:00:20 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 260920 kb
Host smart-25bb6e35-d133-44e0-9089-8e83120f5d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694650668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3694650668
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.734515190
Short name T184
Test name
Test status
Simulation time 150536300 ps
CPU time 34.8 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:02:44 PM PST 24
Peak memory 258884 kb
Host smart-c3164af1-a985-47bb-8f18-776397558846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734515190 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.734515190
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1783178205
Short name T171
Test name
Test status
Simulation time 19217200 ps
CPU time 15.09 seconds
Started Jan 10 01:00:23 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 258708 kb
Host smart-9e9eab19-576e-4b3c-a8ff-708a42eebf02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783178205 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1783178205
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1791190168
Short name T182
Test name
Test status
Simulation time 17991200 ps
CPU time 15.38 seconds
Started Jan 10 01:00:23 PM PST 24
Finished Jan 10 01:02:11 PM PST 24
Peak memory 258768 kb
Host smart-c8166242-4eae-4840-b19c-de625b27f880
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791190168 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1791190168
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.353436133
Short name T45
Test name
Test status
Simulation time 100986800 ps
CPU time 18.93 seconds
Started Jan 10 01:00:15 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 262908 kb
Host smart-6d55e31c-f979-410a-821e-5094fc78eeff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353436133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.353436133
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2264205076
Short name T78
Test name
Test status
Simulation time 1353515100 ps
CPU time 888.03 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:17:07 PM PST 24
Peak memory 261092 kb
Host smart-d34ab03d-6e6b-44a8-955f-ab85c6004399
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264205076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2264205076
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1046202738
Short name T26
Test name
Test status
Simulation time 23637700 ps
CPU time 15.24 seconds
Started Jan 10 01:01:14 PM PST 24
Finished Jan 10 01:02:55 PM PST 24
Peak memory 262960 kb
Host smart-8afe6a7a-3c59-4ae6-9d6a-5e0c50afb6ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046202738 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1046202738
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4162957711
Short name T173
Test name
Test status
Simulation time 28873900 ps
CPU time 14.29 seconds
Started Jan 10 01:00:28 PM PST 24
Finished Jan 10 01:02:00 PM PST 24
Peak memory 258876 kb
Host smart-d62db679-d816-41ee-81cf-82a03d170829
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162957711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.4162957711
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1452176803
Short name T204
Test name
Test status
Simulation time 17387200 ps
CPU time 13.35 seconds
Started Jan 10 01:00:40 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 261088 kb
Host smart-29e78a0a-40f1-40e8-8477-f1b85da0ef4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452176803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1452176803
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2623766665
Short name T72
Test name
Test status
Simulation time 119440600 ps
CPU time 16.01 seconds
Started Jan 10 01:00:43 PM PST 24
Finished Jan 10 01:02:21 PM PST 24
Peak memory 258852 kb
Host smart-c1de7f7a-e800-4c9b-b778-82c05bd42007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623766665 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2623766665
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3295329205
Short name T140
Test name
Test status
Simulation time 23615900 ps
CPU time 15.49 seconds
Started Jan 10 01:00:36 PM PST 24
Finished Jan 10 01:02:24 PM PST 24
Peak memory 258708 kb
Host smart-bf06feb5-1968-479c-8072-a995175cfdef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295329205 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3295329205
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.120546407
Short name T44
Test name
Test status
Simulation time 40745700 ps
CPU time 15.4 seconds
Started Jan 10 01:01:04 PM PST 24
Finished Jan 10 01:02:37 PM PST 24
Peak memory 258852 kb
Host smart-194fa921-4331-4136-b8a8-5b4f1c6ad2ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120546407 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.120546407
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3089181432
Short name T112
Test name
Test status
Simulation time 53564300 ps
CPU time 19.38 seconds
Started Jan 10 01:00:27 PM PST 24
Finished Jan 10 01:02:10 PM PST 24
Peak memory 262880 kb
Host smart-2511535c-0be8-4992-9da7-99f9b7a08c21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089181432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3089181432
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4237873251
Short name T68
Test name
Test status
Simulation time 824782900 ps
CPU time 35.79 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:02:20 PM PST 24
Peak memory 258788 kb
Host smart-9f2942fd-93ce-40fb-b5f5-d855f7892c11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237873251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.4237873251
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.593113646
Short name T186
Test name
Test status
Simulation time 3278922100 ps
CPU time 69.78 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:02:46 PM PST 24
Peak memory 258768 kb
Host smart-4c86ff7b-dea8-4a94-92b6-db2390935e73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593113646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.593113646
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.974005448
Short name T164
Test name
Test status
Simulation time 57280500 ps
CPU time 25.37 seconds
Started Jan 10 12:59:55 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 258856 kb
Host smart-b4199c73-1cfd-4e98-80e5-64b03ac8e376
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974005448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.974005448
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.554120136
Short name T52
Test name
Test status
Simulation time 26718100 ps
CPU time 18.25 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:01:56 PM PST 24
Peak memory 271176 kb
Host smart-27cb309f-340b-4952-b064-858012ebbcd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554120136 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.554120136
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1125941123
Short name T206
Test name
Test status
Simulation time 194217200 ps
CPU time 16.56 seconds
Started Jan 10 12:59:55 PM PST 24
Finished Jan 10 01:01:48 PM PST 24
Peak memory 258764 kb
Host smart-d759abe8-3314-4e74-8896-31c79a5e70cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125941123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.1125941123
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1712823235
Short name T33
Test name
Test status
Simulation time 384567800 ps
CPU time 35.15 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:02:09 PM PST 24
Peak memory 260736 kb
Host smart-feb1e009-f02c-4327-9724-c4c09710f789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712823235 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1712823235
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3791412489
Short name T169
Test name
Test status
Simulation time 21312000 ps
CPU time 13.11 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 258688 kb
Host smart-e7a9728d-fadc-4d64-b9da-21f9a330a092
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791412489 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3791412489
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3957879419
Short name T146
Test name
Test status
Simulation time 40234800 ps
CPU time 15.2 seconds
Started Jan 10 01:00:02 PM PST 24
Finished Jan 10 01:01:53 PM PST 24
Peak memory 258688 kb
Host smart-b680ef74-951b-4255-a2c5-89244508699d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957879419 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3957879419
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.791403907
Short name T85
Test name
Test status
Simulation time 366233800 ps
CPU time 452.16 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:09:02 PM PST 24
Peak memory 262916 kb
Host smart-d280ac4d-9fab-423c-b9b1-58de9049935b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791403907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.791403907
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1916753634
Short name T96
Test name
Test status
Simulation time 93903300 ps
CPU time 13.26 seconds
Started Jan 10 01:00:36 PM PST 24
Finished Jan 10 01:02:44 PM PST 24
Peak memory 260948 kb
Host smart-c7c337f9-1f69-4489-8c0a-a1739a8889fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916753634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
1916753634
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3553468474
Short name T18
Test name
Test status
Simulation time 30868000 ps
CPU time 13.18 seconds
Started Jan 10 01:00:31 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 261048 kb
Host smart-7ad5acd8-ccfb-4040-a517-f7b217965656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553468474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
3553468474
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1745447367
Short name T113
Test name
Test status
Simulation time 17748800 ps
CPU time 13.13 seconds
Started Jan 10 01:00:36 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 260660 kb
Host smart-da42bebe-21dd-48a8-b7fc-6b2b62deb2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745447367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
1745447367
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3045190695
Short name T89
Test name
Test status
Simulation time 84696300 ps
CPU time 13.2 seconds
Started Jan 10 01:01:04 PM PST 24
Finished Jan 10 01:02:42 PM PST 24
Peak memory 261004 kb
Host smart-997d27e0-ad7f-4de1-9529-a4d7b919d3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045190695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
3045190695
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3995599677
Short name T93
Test name
Test status
Simulation time 34570200 ps
CPU time 13.36 seconds
Started Jan 10 01:01:02 PM PST 24
Finished Jan 10 01:02:42 PM PST 24
Peak memory 260928 kb
Host smart-fc8e758a-00c3-4529-83b6-e5b1a360abbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995599677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
3995599677
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1108455576
Short name T115
Test name
Test status
Simulation time 18388400 ps
CPU time 13.4 seconds
Started Jan 10 01:00:31 PM PST 24
Finished Jan 10 01:02:42 PM PST 24
Peak memory 260932 kb
Host smart-23929eec-9894-46fe-aab8-0929bc0876db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108455576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1108455576
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2051809473
Short name T130
Test name
Test status
Simulation time 18505500 ps
CPU time 13.35 seconds
Started Jan 10 01:01:04 PM PST 24
Finished Jan 10 01:02:35 PM PST 24
Peak memory 261184 kb
Host smart-17d902e4-0e9c-4194-99b0-f1b7a72f48fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051809473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2051809473
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3527774030
Short name T152
Test name
Test status
Simulation time 841535300 ps
CPU time 51.05 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:02:35 PM PST 24
Peak memory 258748 kb
Host smart-7621d8f8-d50b-4983-8491-6233ae27c19f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527774030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.3527774030
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.872786
Short name T87
Test name
Test status
Simulation time 2632450700 ps
CPU time 63.08 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:03:34 PM PST 24
Peak memory 258884 kb
Host smart-bbc2dd67-66ca-4482-8fd6-ebab55051af0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_csr_bit_bash.872786
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2687117467
Short name T34
Test name
Test status
Simulation time 64092000 ps
CPU time 25.26 seconds
Started Jan 10 01:00:04 PM PST 24
Finished Jan 10 01:01:59 PM PST 24
Peak memory 258836 kb
Host smart-9eaae5d5-401e-433e-9ff0-5bdb4afdc217
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687117467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.2687117467
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3358727592
Short name T88
Test name
Test status
Simulation time 119846600 ps
CPU time 16.41 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 277692 kb
Host smart-f0e7a22a-aaa2-47eb-a066-0a2164e31e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358727592 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.3358727592
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2358412605
Short name T211
Test name
Test status
Simulation time 42747000 ps
CPU time 16.28 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:58 PM PST 24
Peak memory 258756 kb
Host smart-1c5d2057-838f-4220-b5af-9a8c7e09779d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358412605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.2358412605
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.559524221
Short name T57
Test name
Test status
Simulation time 24349000 ps
CPU time 13.32 seconds
Started Jan 10 01:00:01 PM PST 24
Finished Jan 10 01:01:48 PM PST 24
Peak memory 260828 kb
Host smart-cd5ef25d-f22d-4a6d-8af1-52382d4b0580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559524221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.559524221
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1305236058
Short name T124
Test name
Test status
Simulation time 47931300 ps
CPU time 13.12 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:48 PM PST 24
Peak memory 260976 kb
Host smart-7a75be3c-cc38-483e-bd05-1fb7818b3156
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305236058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1305236058
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3347295805
Short name T13
Test name
Test status
Simulation time 36709100 ps
CPU time 17.53 seconds
Started Jan 10 01:00:00 PM PST 24
Finished Jan 10 01:01:52 PM PST 24
Peak memory 258796 kb
Host smart-2dcc6455-62c8-4227-9f19-285e8e74ec79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347295805 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3347295805
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3563377069
Short name T145
Test name
Test status
Simulation time 14526800 ps
CPU time 12.87 seconds
Started Jan 10 01:00:04 PM PST 24
Finished Jan 10 01:01:46 PM PST 24
Peak memory 258712 kb
Host smart-d1b6d741-181f-47e6-b0e1-a146ec15c440
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563377069 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3563377069
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.802540383
Short name T149
Test name
Test status
Simulation time 17157200 ps
CPU time 13.05 seconds
Started Jan 10 01:00:03 PM PST 24
Finished Jan 10 01:01:42 PM PST 24
Peak memory 258724 kb
Host smart-fda49f27-81bd-4cf9-82d9-475539bfff85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802540383 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.802540383
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1668153883
Short name T193
Test name
Test status
Simulation time 1866998900 ps
CPU time 748.59 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:14:22 PM PST 24
Peak memory 262948 kb
Host smart-1de40f54-de4b-426b-8c1a-3aad4cc17431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668153883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1668153883
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2209903132
Short name T99
Test name
Test status
Simulation time 25580700 ps
CPU time 13.6 seconds
Started Jan 10 01:00:31 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 261000 kb
Host smart-675d7c97-c2e4-4573-bf61-1dbb2e3f295e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209903132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
2209903132
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2026892894
Short name T110
Test name
Test status
Simulation time 64550300 ps
CPU time 13.2 seconds
Started Jan 10 01:00:52 PM PST 24
Finished Jan 10 01:02:38 PM PST 24
Peak memory 260928 kb
Host smart-54eb9ca1-12ce-4699-80e0-1b3ff500b90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026892894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2026892894
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.4020112342
Short name T16
Test name
Test status
Simulation time 17415100 ps
CPU time 13.17 seconds
Started Jan 10 01:00:36 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 260780 kb
Host smart-1f89f5c5-ebe3-44ef-a517-116d6abc04b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020112342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
4020112342
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.570450526
Short name T178
Test name
Test status
Simulation time 35106800 ps
CPU time 13.18 seconds
Started Jan 10 01:00:40 PM PST 24
Finished Jan 10 01:02:15 PM PST 24
Peak memory 260836 kb
Host smart-582101ce-60d8-4832-a897-a5783ebc948b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570450526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.570450526
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3857378066
Short name T187
Test name
Test status
Simulation time 21327400 ps
CPU time 13.07 seconds
Started Jan 10 01:01:13 PM PST 24
Finished Jan 10 01:02:54 PM PST 24
Peak memory 260936 kb
Host smart-e27c05d2-1d8b-471f-8c08-d6308eb94759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857378066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
3857378066
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3513821715
Short name T129
Test name
Test status
Simulation time 25362400 ps
CPU time 13.16 seconds
Started Jan 10 01:01:02 PM PST 24
Finished Jan 10 01:02:42 PM PST 24
Peak memory 261076 kb
Host smart-d4788018-d955-410e-8a13-01b8a5ef0bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513821715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
3513821715
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1212826463
Short name T128
Test name
Test status
Simulation time 223267400 ps
CPU time 13.94 seconds
Started Jan 10 01:00:23 PM PST 24
Finished Jan 10 01:02:43 PM PST 24
Peak memory 260856 kb
Host smart-dc57fa17-67c8-476a-9749-61832b4b184a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212826463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1212826463
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3623523918
Short name T157
Test name
Test status
Simulation time 423573400 ps
CPU time 31.52 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:02:25 PM PST 24
Peak memory 258892 kb
Host smart-1cc96793-81bd-48e0-9d3c-6b9cefb2e2d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623523918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.3623523918
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3071906535
Short name T210
Test name
Test status
Simulation time 421519900 ps
CPU time 37.39 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:02:13 PM PST 24
Peak memory 258864 kb
Host smart-7ec273f9-c8db-4964-8bae-0d2a6044cd9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071906535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.3071906535
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.4141710236
Short name T63
Test name
Test status
Simulation time 35100600 ps
CPU time 44.39 seconds
Started Jan 10 01:00:17 PM PST 24
Finished Jan 10 01:02:43 PM PST 24
Peak memory 258856 kb
Host smart-0ad47a1a-4f79-4be4-b6b8-5f1f9a17fb1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141710236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.4141710236
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2595447343
Short name T73
Test name
Test status
Simulation time 234658300 ps
CPU time 16.24 seconds
Started Jan 10 01:00:20 PM PST 24
Finished Jan 10 01:02:21 PM PST 24
Peak memory 262896 kb
Host smart-14c70ebb-1711-4b24-a85a-bee6c985be3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595447343 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.2595447343
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1090778756
Short name T119
Test name
Test status
Simulation time 106758700 ps
CPU time 13.36 seconds
Started Jan 10 01:00:41 PM PST 24
Finished Jan 10 01:02:22 PM PST 24
Peak memory 261024 kb
Host smart-926a5566-100a-4a3d-8f7e-652c3770ac90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090778756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
090778756
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.392586064
Short name T40
Test name
Test status
Simulation time 28171900 ps
CPU time 13.46 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:02:32 PM PST 24
Peak memory 262368 kb
Host smart-32df991f-3025-43c2-92ef-421962a6276d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392586064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.392586064
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4280422420
Short name T202
Test name
Test status
Simulation time 310052200 ps
CPU time 34.39 seconds
Started Jan 10 01:00:07 PM PST 24
Finished Jan 10 01:02:11 PM PST 24
Peak memory 258896 kb
Host smart-224598b4-5cfd-46ee-a36e-a3cf57cc4a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280422420 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.4280422420
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3996759944
Short name T177
Test name
Test status
Simulation time 12924600 ps
CPU time 15.24 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:01:56 PM PST 24
Peak memory 258844 kb
Host smart-4087cad1-1584-4627-9531-32871aaf5b0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996759944 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3996759944
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.56240224
Short name T150
Test name
Test status
Simulation time 21701000 ps
CPU time 12.9 seconds
Started Jan 10 01:00:22 PM PST 24
Finished Jan 10 01:02:38 PM PST 24
Peak memory 258648 kb
Host smart-bacfcae4-5274-4e24-b129-fbf4099edf2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56240224 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.56240224
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2043589137
Short name T101
Test name
Test status
Simulation time 35357000 ps
CPU time 15.91 seconds
Started Jan 10 01:00:12 PM PST 24
Finished Jan 10 01:02:09 PM PST 24
Peak memory 262960 kb
Host smart-dac84df7-b944-4adf-94fb-9c3fd572d730
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043589137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
043589137
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3871226504
Short name T83
Test name
Test status
Simulation time 674623500 ps
CPU time 381.7 seconds
Started Jan 10 01:00:18 PM PST 24
Finished Jan 10 01:08:03 PM PST 24
Peak memory 260060 kb
Host smart-229e3755-97e9-48b4-a7d5-43c1dd54ae61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871226504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.3871226504
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3614282315
Short name T108
Test name
Test status
Simulation time 21431100 ps
CPU time 13.28 seconds
Started Jan 10 01:00:46 PM PST 24
Finished Jan 10 01:02:17 PM PST 24
Peak memory 261032 kb
Host smart-64e30a25-1589-4f6f-8f80-6c0d740d6f3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614282315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
3614282315
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2368970841
Short name T97
Test name
Test status
Simulation time 16166100 ps
CPU time 13.3 seconds
Started Jan 10 01:00:35 PM PST 24
Finished Jan 10 01:02:36 PM PST 24
Peak memory 260920 kb
Host smart-22d035ad-16b8-4b41-9605-0d3593051835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368970841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2368970841
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1062909425
Short name T107
Test name
Test status
Simulation time 57357100 ps
CPU time 13.29 seconds
Started Jan 10 01:00:35 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 260928 kb
Host smart-58bff468-ba4f-473b-9d0c-7d564b8263fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062909425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
1062909425
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1206081104
Short name T77
Test name
Test status
Simulation time 46436000 ps
CPU time 13.37 seconds
Started Jan 10 01:01:09 PM PST 24
Finished Jan 10 01:02:52 PM PST 24
Peak memory 260828 kb
Host smart-b4a06e8d-4e5d-43c8-86f1-0184426fdbf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206081104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
1206081104
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2637883350
Short name T29
Test name
Test status
Simulation time 24003500 ps
CPU time 13.3 seconds
Started Jan 10 01:00:52 PM PST 24
Finished Jan 10 01:02:38 PM PST 24
Peak memory 260960 kb
Host smart-dd0e90c9-e00b-41fb-aa2a-26d95fb45df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637883350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
2637883350
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2202245528
Short name T191
Test name
Test status
Simulation time 27343600 ps
CPU time 13.25 seconds
Started Jan 10 01:01:05 PM PST 24
Finished Jan 10 01:02:34 PM PST 24
Peak memory 260936 kb
Host smart-57222a08-30a0-4201-abf4-b70328bc43c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202245528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2202245528
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2713970276
Short name T95
Test name
Test status
Simulation time 85211200 ps
CPU time 13.24 seconds
Started Jan 10 01:01:03 PM PST 24
Finished Jan 10 01:02:37 PM PST 24
Peak memory 261416 kb
Host smart-affe86b3-edd7-4f3e-94dc-15c3ef3f7136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713970276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
2713970276
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2412847754
Short name T117
Test name
Test status
Simulation time 14165000 ps
CPU time 13.42 seconds
Started Jan 10 01:00:31 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 261208 kb
Host smart-4e5c497f-cafb-4b42-961a-79b4046dc19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412847754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2412847754
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2592520075
Short name T94
Test name
Test status
Simulation time 14457500 ps
CPU time 13.16 seconds
Started Jan 10 01:00:36 PM PST 24
Finished Jan 10 01:02:44 PM PST 24
Peak memory 261184 kb
Host smart-3c8ff625-6e43-4e80-afdf-c4f7ef3d9467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592520075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2592520075
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.596670015
Short name T133
Test name
Test status
Simulation time 78976600 ps
CPU time 17.49 seconds
Started Jan 10 01:00:46 PM PST 24
Finished Jan 10 01:02:36 PM PST 24
Peak memory 271292 kb
Host smart-ac30d6a6-bd50-43d4-81ff-b787df1c8c32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596670015 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.596670015
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.142292294
Short name T11
Test name
Test status
Simulation time 130913900 ps
CPU time 15.75 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:01:51 PM PST 24
Peak memory 258856 kb
Host smart-ad539660-ed05-49d7-98d5-e8eb10c09f28
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142292294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_csr_rw.142292294
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1688144772
Short name T66
Test name
Test status
Simulation time 152503000 ps
CPU time 19.21 seconds
Started Jan 10 01:00:10 PM PST 24
Finished Jan 10 01:02:28 PM PST 24
Peak memory 258824 kb
Host smart-ac229514-8f69-47a6-8f73-ca430b02a4d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688144772 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1688144772
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2931497069
Short name T137
Test name
Test status
Simulation time 18795200 ps
CPU time 15.17 seconds
Started Jan 10 01:00:13 PM PST 24
Finished Jan 10 01:02:46 PM PST 24
Peak memory 258780 kb
Host smart-a91ca1e6-3897-44a5-8603-a87543c6fe4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931497069 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.2931497069
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.4054727106
Short name T3
Test name
Test status
Simulation time 17444800 ps
CPU time 15.32 seconds
Started Jan 10 01:00:13 PM PST 24
Finished Jan 10 01:02:01 PM PST 24
Peak memory 258776 kb
Host smart-071d2775-3e35-47df-a73b-29a96ae94fb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054727106 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.4054727106
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4156209152
Short name T203
Test name
Test status
Simulation time 617560800 ps
CPU time 19.8 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:02:06 PM PST 24
Peak memory 262912 kb
Host smart-532880b2-16e1-418e-8811-ca9c491c295e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156209152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.4
156209152
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3886051806
Short name T31
Test name
Test status
Simulation time 399880700 ps
CPU time 451.61 seconds
Started Jan 10 01:00:10 PM PST 24
Finished Jan 10 01:09:37 PM PST 24
Peak memory 258776 kb
Host smart-6c67ef25-eef1-40b1-a629-e1e4094eba2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886051806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.3886051806
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2463423725
Short name T48
Test name
Test status
Simulation time 33687900 ps
CPU time 19.63 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:01:58 PM PST 24
Peak memory 276632 kb
Host smart-0191b57f-d1e3-42e1-ba6d-03e88d0fe41f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463423725 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2463423725
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1431118254
Short name T161
Test name
Test status
Simulation time 104453900 ps
CPU time 16.74 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 258844 kb
Host smart-d4d9ee9c-0f27-4c40-a055-d9b03d16de5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431118254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1431118254
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1534478610
Short name T172
Test name
Test status
Simulation time 61400400 ps
CPU time 16.79 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:01:57 PM PST 24
Peak memory 258728 kb
Host smart-5b1819f3-e654-4451-893f-00a2948765f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534478610 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1534478610
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3129241449
Short name T144
Test name
Test status
Simulation time 17668300 ps
CPU time 12.99 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:49 PM PST 24
Peak memory 258840 kb
Host smart-dcf98801-52d2-4272-a444-21762f549d74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129241449 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3129241449
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1905152316
Short name T148
Test name
Test status
Simulation time 14934800 ps
CPU time 15.13 seconds
Started Jan 10 01:00:11 PM PST 24
Finished Jan 10 01:01:51 PM PST 24
Peak memory 258708 kb
Host smart-6992bd16-3c9b-467e-8167-c94133a184e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905152316 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1905152316
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2062586188
Short name T207
Test name
Test status
Simulation time 93429300 ps
CPU time 18.62 seconds
Started Jan 10 01:00:10 PM PST 24
Finished Jan 10 01:02:20 PM PST 24
Peak memory 262920 kb
Host smart-3ffb3e15-a36f-4aeb-a0fd-850d576b7273
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062586188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
062586188
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.818552902
Short name T6
Test name
Test status
Simulation time 41568000 ps
CPU time 17.36 seconds
Started Jan 10 01:00:16 PM PST 24
Finished Jan 10 01:02:04 PM PST 24
Peak memory 271196 kb
Host smart-3722c384-bacd-4762-ba8a-0150d8776458
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818552902 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.818552902
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4019834166
Short name T189
Test name
Test status
Simulation time 135534500 ps
CPU time 14.7 seconds
Started Jan 10 01:00:05 PM PST 24
Finished Jan 10 01:02:02 PM PST 24
Peak memory 258940 kb
Host smart-f7a2d012-1d97-4374-a6a7-6875eb83a84c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019834166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.4019834166
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2559949304
Short name T155
Test name
Test status
Simulation time 155581000 ps
CPU time 33.47 seconds
Started Jan 10 01:00:53 PM PST 24
Finished Jan 10 01:02:55 PM PST 24
Peak memory 258764 kb
Host smart-8a07255c-08af-4db4-858e-086f85e16856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559949304 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2559949304
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4294019878
Short name T142
Test name
Test status
Simulation time 32821200 ps
CPU time 12.79 seconds
Started Jan 10 01:00:14 PM PST 24
Finished Jan 10 01:01:51 PM PST 24
Peak memory 258832 kb
Host smart-81c4d901-35fe-4456-8ff2-8a93af3fc756
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294019878 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.4294019878
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3894816197
Short name T188
Test name
Test status
Simulation time 19010100 ps
CPU time 12.9 seconds
Started Jan 10 01:00:07 PM PST 24
Finished Jan 10 01:01:49 PM PST 24
Peak memory 258808 kb
Host smart-d59883e1-1d6c-4ca5-a977-e15b2eec3f01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894816197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3894816197
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2857345895
Short name T195
Test name
Test status
Simulation time 25609500 ps
CPU time 15.63 seconds
Started Jan 10 01:00:28 PM PST 24
Finished Jan 10 01:02:07 PM PST 24
Peak memory 275552 kb
Host smart-e264425b-9dca-45c1-a36c-508463544642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857345895 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2857345895
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2657629030
Short name T205
Test name
Test status
Simulation time 153787300 ps
CPU time 13.95 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:02:19 PM PST 24
Peak memory 262920 kb
Host smart-027ca8bf-c18f-4388-bb8a-2da67d2c0b89
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657629030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2657629030
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2310405992
Short name T121
Test name
Test status
Simulation time 62702200 ps
CPU time 13.04 seconds
Started Jan 10 01:00:48 PM PST 24
Finished Jan 10 01:02:27 PM PST 24
Peak memory 260912 kb
Host smart-fd09c49a-62b0-422c-a1d2-edd37dbf714d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310405992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
310405992
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1423066199
Short name T55
Test name
Test status
Simulation time 512918900 ps
CPU time 17.21 seconds
Started Jan 10 01:00:09 PM PST 24
Finished Jan 10 01:02:10 PM PST 24
Peak memory 258860 kb
Host smart-aff40dbf-b3ac-4c94-bd87-db49996f0858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423066199 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.1423066199
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2702472588
Short name T141
Test name
Test status
Simulation time 31501700 ps
CPU time 15.27 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:01:55 PM PST 24
Peak memory 258704 kb
Host smart-8e2e5ed0-bce5-419f-983c-b514c1d98e4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702472588 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2702472588
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.157522051
Short name T154
Test name
Test status
Simulation time 14994200 ps
CPU time 15.4 seconds
Started Jan 10 01:00:19 PM PST 24
Finished Jan 10 01:02:09 PM PST 24
Peak memory 258716 kb
Host smart-6c931215-ddb7-47ec-95d0-c2bb2492b88c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157522051 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.157522051
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3928801849
Short name T51
Test name
Test status
Simulation time 797900000 ps
CPU time 375.33 seconds
Started Jan 10 01:00:13 PM PST 24
Finished Jan 10 01:08:43 PM PST 24
Peak memory 262868 kb
Host smart-d4e85eb8-03ec-436c-948f-e6c79e5778ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928801849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.3928801849
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2336807011
Short name T132
Test name
Test status
Simulation time 41126400 ps
CPU time 17.51 seconds
Started Jan 10 01:00:13 PM PST 24
Finished Jan 10 01:02:16 PM PST 24
Peak memory 269060 kb
Host smart-84a63f36-badf-4309-af17-d87385a68e30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336807011 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2336807011
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2972464735
Short name T175
Test name
Test status
Simulation time 102996100 ps
CPU time 14.72 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:02:06 PM PST 24
Peak memory 258836 kb
Host smart-27719ba8-0095-4d21-bb8f-317b10a55221
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972464735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.2972464735
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1178604569
Short name T19
Test name
Test status
Simulation time 53304300 ps
CPU time 13.13 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:02:18 PM PST 24
Peak memory 261176 kb
Host smart-34c587e8-8685-4e3b-9224-de61d6188b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178604569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
178604569
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3861147747
Short name T165
Test name
Test status
Simulation time 82414800 ps
CPU time 33.57 seconds
Started Jan 10 01:00:06 PM PST 24
Finished Jan 10 01:03:02 PM PST 24
Peak memory 258828 kb
Host smart-f26386bc-dac2-4e44-8d36-dc21fcd4164d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861147747 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3861147747
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2790805604
Short name T153
Test name
Test status
Simulation time 11733700 ps
CPU time 13.1 seconds
Started Jan 10 01:00:47 PM PST 24
Finished Jan 10 01:02:12 PM PST 24
Peak memory 258700 kb
Host smart-93049ce7-73cf-428c-8336-85bb10a4df0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790805604 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2790805604
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3431731431
Short name T58
Test name
Test status
Simulation time 14614100 ps
CPU time 13.44 seconds
Started Jan 10 01:00:51 PM PST 24
Finished Jan 10 01:02:27 PM PST 24
Peak memory 258800 kb
Host smart-4dc05527-8ff9-436c-a9f8-9ada2fcab47a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431731431 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3431731431
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1344427218
Short name T50
Test name
Test status
Simulation time 763419700 ps
CPU time 891.1 seconds
Started Jan 10 01:00:12 PM PST 24
Finished Jan 10 01:16:45 PM PST 24
Peak memory 260196 kb
Host smart-0dfd01a2-08cf-4f81-b29b-920403ea5e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344427218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1344427218
Directory /workspace/9.flash_ctrl_tl_intg_err/latest
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