cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | smoke_hw | flash_ctrl_smoke_hw | 0 | 5 | 0.00 | ||
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.540s | 309.991us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.163m | 3.279ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 53.970s | 2.328ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.630s | 33.688us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 |
| flash_ctrl_csr_aliasing | 53.970s | 2.328ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.180s | 53.128us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.530s | 17.680us | 5 | 5 | 100.00 |
| V1 | TOTAL | 64 | 120 | 53.33 | |||
| V2 | sw_op | flash_ctrl_sw_op | 0 | 5 | 0.00 | ||
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 0 | 5 | 0.00 | ||
| V2 | rma_hw_if | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| flash_ctrl_hw_rma_reset | 0 | 20 | 0.00 | ||||
| flash_ctrl_lcmgr_intg | 0 | 20 | 0.00 | ||||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 0 | 5 | 0.00 | ||
| V2 | erase_suspend | flash_ctrl_erase_suspend | 0 | 5 | 0.00 | ||
| V2 | program_reset | flash_ctrl_prog_reset | 0 | 30 | 0.00 | ||
| V2 | full_memory_access | flash_ctrl_full_mem_access | 0 | 5 | 0.00 | ||
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 0 | 5 | 0.00 | ||
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 0 | 40 | 0.00 | ||
| flash_ctrl_rw_evict_all_en | 0 | 40 | 0.00 | ||||
| flash_ctrl_re_evict | 0 | 20 | 0.00 | ||||
| V2 | host_arb | flash_ctrl_phy_arb | 0 | 20 | 0.00 | ||
| V2 | host_interleave | flash_ctrl_phy_arb | 0 | 20 | 0.00 | ||
| V2 | memory_protection | flash_ctrl_mp_regions | 0 | 20 | 0.00 | ||
| V2 | fetch_code | flash_ctrl_fetch_code | 0 | 10 | 0.00 | ||
| V2 | all_partitions | flash_ctrl_rand_ops | 0 | 20 | 0.00 | ||
| V2 | error_mp | flash_ctrl_error_mp | 0 | 10 | 0.00 | ||
| V2 | error_prog_win | flash_ctrl_error_prog_win | 0 | 10 | 0.00 | ||
| V2 | error_prog_type | flash_ctrl_error_prog_type | 0 | 5 | 0.00 | ||
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 0 | 20 | 0.00 | ||
| V2 | read_write_overflow | flash_ctrl_oversize_error | 0 | 5 | 0.00 | ||
| V2 | flash_ctrl_disable | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2 | flash_ctrl_connect | flash_ctrl_connect | 0 | 80 | 0.00 | ||
| V2 | stress_all | flash_ctrl_stress_all | 0 | 5 | 0.00 | ||
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 0 | 50 | 0.00 | ||
| flash_ctrl_otp_reset | 0 | 80 | 0.00 | ||||
| V2 | isolation_partition | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| V2 | interrupts | flash_ctrl_intr_rd | 0 | 40 | 0.00 | ||
| flash_ctrl_intr_wr | 0 | 10 | 0.00 | ||||
| flash_ctrl_intr_rd_slow_flash | 0 | 40 | 0.00 | ||||
| flash_ctrl_intr_wr_slow_flash | 0 | 10 | 0.00 | ||||
| V2 | invalid_op | flash_ctrl_invalid_op | 0 | 20 | 0.00 | ||
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 0 | 5 | 0.00 | ||
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 0 | 5 | 0.00 | ||
| flash_ctrl_ro_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_rw_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_derr_detect | 0 | 5 | 0.00 | ||||
| flash_ctrl_integrity | 0 | 5 | 0.00 | ||||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 0 | 5 | 0.00 | ||
| flash_ctrl_ro_serr | 0 | 10 | 0.00 | ||||
| flash_ctrl_rw_serr | 0 | 10 | 0.00 | ||||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 0 | 5 | 0.00 | ||
| V2 | singlebit_err_address | flash_ctrl_serr_address | 0 | 5 | 0.00 | ||
| V2 | scramble | flash_ctrl_wo | 0 | 20 | 0.00 | ||
| flash_ctrl_write_word_sweep | 0 | 1 | 0.00 | ||||
| flash_ctrl_read_word_sweep | 0 | 1 | 0.00 | ||||
| flash_ctrl_ro | 0 | 20 | 0.00 | ||||
| flash_ctrl_rw | 0 | 20 | 0.00 | ||||
| V2 | filesystem_support | flash_ctrl_fs_sup | 0 | 5 | 0.00 | ||
| V2 | rma_write_process_error | flash_ctrl_rma_err | 0 | 3 | 0.00 | ||
| flash_ctrl_hw_prog_rma_wipe_err | 0 | 20 | 0.00 | ||||
| V2 | alert_test | flash_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | flash_ctrl_intr_test | 13.940s | 223.267us | 49 | 50 | 98.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 19.800s | 617.561us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 19.800s | 617.561us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.540s | 309.991us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 | ||
| flash_ctrl_csr_aliasing | 53.970s | 2.328ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.150s | 384.568us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.540s | 309.991us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 | ||
| flash_ctrl_csr_aliasing | 53.970s | 2.328ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.150s | 384.568us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 89 | 1013 | 8.79 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 15.530s | 29.393us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| flash_ctrl_tl_intg_err | 14.854m | 343.906us | 18 | 20 | 90.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 14.854m | 343.906us | 18 | 20 | 90.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 14.854m | 343.906us | 18 | 20 | 90.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 0 | 3 | 0.00 | ||
| flash_ctrl_wr_intg | 0 | 3 | 0.00 | ||||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 0 | 80 | 0.00 | ||
| flash_ctrl_disable | 0 | 50 | 0.00 | ||||
| flash_ctrl_sec_info_access | 0 | 50 | 0.00 | ||||
| flash_ctrl_connect | 0 | 80 | 0.00 | ||||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 0 | 5 | 0.00 | ||
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.320s | 744.838us | 19 | 20 | 95.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 15.490s | 23.616us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 0 | 3 | 0.00 | ||
| flash_ctrl_access_after_disable | 0 | 3 | 0.00 | ||||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 0 | 10 | 0.00 | ||
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 0 | 10 | 0.00 | ||
| flash_ctrl_rw_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_integrity | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 58 | 144 | 40.28 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 211 | 1278 | 16.51 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 6 | 66.67 |
| V2 | 55 | 55 | 2 | 3.64 |
| V2S | 12 | 12 | 2 | 16.67 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 55.82 | 51.96 | 51.79 | 49.37 | 0.00 | 66.43 | 99.33 | 71.84 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 532 failures:
0.flash_ctrl_smoke.102233026647619544221368885705597843299122865931564243804116067231384651643035
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest/run.log
1.flash_ctrl_smoke.10805884952694237184334478837784683760471586585665215380250744225581333919115
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest/run.log
... and 15 more failures.
0.flash_ctrl_rand_ops.69418966738667149970891537270345503018819036985317520323510480402474554706134
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest/run.log
1.flash_ctrl_rand_ops.65098427485798910873406362495881315643654473424620765215238499067436227788745
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest/run.log
... and 14 more failures.
0.flash_ctrl_host_dir_rd.18326626442642687862533872553659671949020362477104045012786581570125770508665
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest/run.log
1.flash_ctrl_host_dir_rd.9872977414562947071474441932920954373072627901422447766147378874485865155035
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest/run.log
... and 2 more failures.
0.flash_ctrl_phy_arb.76617883662002376486316563119649022735807187017139874837696638160338676233921
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest/run.log
1.flash_ctrl_phy_arb.86093088887194087932050521428919717997109576218776738120529436609380951756270
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest/run.log
... and 5 more failures.
0.flash_ctrl_erase_suspend.53686186819675332344926253105041016968231304980538927398607316418251798565332
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest/run.log
1.flash_ctrl_erase_suspend.15742364777997314372172638766630673731057153047827557318142221270427196392957
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest/run.log
... and 2 more failures.
Job killed most likely because its dependent job failed. has 531 failures:
Test flash_ctrl_smoke_hw has 4 failures.
0.flash_ctrl_smoke_hw.105906150043329270786101220060518392061897158403303870753600579239785994576854
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest/run.log
1.flash_ctrl_smoke_hw.6015829642957653348331407989375896951248350728542321930559750045438740408727
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest/run.log
... and 2 more failures.
Test flash_ctrl_sw_op has 4 failures.
0.flash_ctrl_sw_op.52633983712503177232665193699928724616208771830160715785984709847026524132400
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest/run.log
1.flash_ctrl_sw_op.48865958078264968468722544849775979768974481990966921615816309877147891043367
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest/run.log
... and 2 more failures.
Test flash_ctrl_rd_buff_evict has 4 failures.
0.flash_ctrl_rd_buff_evict.79867435142518241151310630567987744661094267810825042750869780641815322468343
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest/run.log
1.flash_ctrl_rd_buff_evict.60038315755291021063427797778434192157750627555243728722536439649774467728243
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest/run.log
... and 2 more failures.
Test flash_ctrl_hw_sec_otp has 17 failures.
0.flash_ctrl_hw_sec_otp.90915433252517754508241405754155686407387157519304873771721273250853412194527
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest/run.log
1.flash_ctrl_hw_sec_otp.87177946633269663269313895618902569446748749490140798728937833939163650512082
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest/run.log
... and 15 more failures.
Test flash_ctrl_hw_rma has 2 failures.
0.flash_ctrl_hw_rma.38314811151751998362973352767128592851309809818920968710454267480946989033292
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest/run.log
1.flash_ctrl_hw_rma.51699667155707934612637815765473718384431962295814166011500946099994795864605
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest/run.log
... and 57 more tests.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
Test flash_ctrl_tl_intg_err has 2 failures.
0.flash_ctrl_tl_intg_err.57014918031468977158084921062676965554744573973560370773806341968730656652188
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/0.flash_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527561116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.1527561116
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
10.flash_ctrl_tl_intg_err.15879000714277129500282237058763214443629571172539940877135163578315468024753
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/10.flash_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239709105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.239709105
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:00 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test flash_ctrl_csr_rw has 1 failures.
4.flash_ctrl_csr_rw.73100010533843264825576303568257917873759334353098433740974942543749688087059
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest/run.log
[make]: simulate
cd /workspace/4.flash_ctrl_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942587411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.2942587411
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:00 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test flash_ctrl_intr_test has 1 failures.
6.flash_ctrl_intr_test.87076548469516200205964318018151082979769213975406631172525014789900362763201
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest/run.log
[make]: simulate
cd /workspace/6.flash_ctrl_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744227265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1744227265
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:00 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255