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 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T45,T46
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T124,T132,T266
1	1	1	Covered	T47,T51,T48

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T45,T46
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T131,T132,T273
1	1	1	Covered	T47,T50,T48

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T45,T46
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T131,T266,T267
1	1	1	Covered	T47,T51,T48

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T45,T46
1	0	1	Covered	T12,T47,T50
1	1	0	Covered	T274
1	1	1	Covered	T47,T50,T51

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T12,T45,T46