Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	316310	1		T48	5		T49	5		T50	1
all_values[1]	316310	1		T48	5		T49	5		T50	1
all_values[2]	316310	1		T48	5		T49	5		T50	1
all_values[3]	316310	1		T48	5		T49	5		T50	1
all_values[4]	316310	1		T48	5		T49	5		T50	1
all_values[5]	316310	1		T48	5		T49	5		T50	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10202	1		T48	11		T49	17		T50	6
auto[1]	1887658	1		T48	19		T49	13		T119	25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1533013	1		T48	14		T49	18		T50	6
auto[1]	364847	1		T48	16		T49	12		T119	11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1276	1		T48	1		T49	2		T50	1
all_values[0]	auto[0]	auto[1]	444	1		T48	1		T49	2		T128	2
all_values[0]	auto[1]	auto[0]	252374	1		T48	1		T49	1		T119	7
all_values[0]	auto[1]	auto[1]	62216	1		T48	2		T128	1		T131	2
all_values[1]	auto[0]	auto[0]	1618	1		T50	1		T119	4		T120	4
all_values[1]	auto[0]	auto[1]	76	1		T49	1		T119	2		T120	1
all_values[1]	auto[1]	auto[0]	250759	1		T48	3		T49	1		T119	1
all_values[1]	auto[1]	auto[1]	63857	1		T48	2		T49	3		T119	1
all_values[2]	auto[0]	auto[0]	1546	1		T49	1		T50	1		T119	2
all_values[2]	auto[0]	auto[1]	143	1		T129	1		T131	1		T203	3
all_values[2]	auto[1]	auto[0]	304403	1		T48	1		T49	2		T119	4
all_values[2]	auto[1]	auto[1]	10218	1		T48	4		T49	2		T119	2
all_values[3]	auto[0]	auto[0]	1552	1		T48	1		T49	4		T50	1
all_values[3]	auto[0]	auto[1]	145	1		T119	3		T128	1		T129	3
all_values[3]	auto[1]	auto[0]	184381	1		T48	3		T49	1		T119	2
all_values[3]	auto[1]	auto[1]	130232	1		T48	1		T119	1		T128	1
all_values[4]	auto[0]	auto[0]	1184	1		T48	3		T49	2		T50	1
all_values[4]	auto[0]	auto[1]	517	1		T48	1		T49	2		T131	2
all_values[4]	auto[1]	auto[0]	217822	1		T49	1		T119	2		T120	2
all_values[4]	auto[1]	auto[1]	96787	1		T48	1		T120	2		T131	2
all_values[5]	auto[0]	auto[0]	1547	1		T48	1		T49	1		T50	1
all_values[5]	auto[0]	auto[1]	154	1		T48	3		T49	2		T119	1
all_values[5]	auto[1]	auto[0]	314551	1		T49	2		T119	4		T120	1
all_values[5]	auto[1]	auto[1]	58	1		T48	1		T119	1		T128	3