Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T22 |
6 |
|
T56 |
6 |
|
T95 |
4 |
| others[1] |
110 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T22 |
4 |
| others[2] |
93 |
1 |
|
T8 |
1 |
|
T22 |
5 |
|
T56 |
1 |
| others[3] |
189 |
1 |
|
T2 |
1 |
|
T22 |
9 |
|
T56 |
6 |
| false |
44 |
1 |
|
T56 |
1 |
|
T95 |
2 |
|
T333 |
1 |
| true |
6318 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T8 |
1 |
|
T24 |
1 |
|
T22 |
8 |
| others[1] |
238 |
1 |
|
T22 |
9 |
|
T51 |
1 |
|
T56 |
8 |
| others[2] |
232 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
3 |
| others[3] |
375 |
1 |
|
T2 |
1 |
|
T19 |
2 |
|
T22 |
19 |
| false |
129 |
1 |
|
T19 |
1 |
|
T22 |
5 |
|
T33 |
1 |
| true |
5654 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T50 |
1 |
|
T131 |
1 |
|
T254 |
1 |
| others[1] |
1049 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T119 |
1 |
| others[2] |
1057 |
1 |
|
T128 |
1 |
|
T113 |
1 |
|
T114 |
1 |
| others[3] |
1756 |
1 |
|
T46 |
1 |
|
T307 |
1 |
|
T339 |
1 |
| false |
511 |
1 |
|
T308 |
1 |
|
T248 |
1 |
|
T127 |
1 |
| true |
1420 |
1 |
|
T19 |
6 |
|
T20 |
1 |
|
T28 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T19 |
1 |
|
T28 |
1 |
|
T22 |
17 |
| others[1] |
227 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T22 |
9 |
| others[2] |
238 |
1 |
|
T22 |
12 |
|
T51 |
1 |
|
T56 |
9 |
| others[3] |
388 |
1 |
|
T2 |
1 |
|
T19 |
5 |
|
T22 |
9 |
| false |
126 |
1 |
|
T20 |
1 |
|
T28 |
1 |
|
T22 |
8 |
| true |
5640 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T28 |
1 |
|
T22 |
10 |
|
T56 |
10 |
| others[1] |
182 |
1 |
|
T2 |
1 |
|
T22 |
9 |
|
T56 |
6 |
| others[2] |
222 |
1 |
|
T3 |
1 |
|
T22 |
8 |
|
T73 |
1 |
| others[3] |
379 |
1 |
|
T1 |
1 |
|
T28 |
1 |
|
T22 |
16 |
| false |
105 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T22 |
6 |
| true |
5751 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T126 |
1 |
| others[1] |
1219 |
1 |
|
T128 |
1 |
|
T129 |
1 |
|
T113 |
1 |
| others[2] |
1243 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T114 |
1 |
| others[3] |
2070 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T131 |
1 |
| false |
627 |
1 |
|
T46 |
1 |
|
T337 |
1 |
|
T342 |
1 |
| true |
422 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T254 |
1 |
|
T117 |
1 |
|
T338 |
1 |
| others[1] |
1260 |
1 |
|
T46 |
1 |
|
T308 |
1 |
|
T204 |
1 |
| others[2] |
1231 |
1 |
|
T113 |
1 |
|
T307 |
1 |
|
T341 |
1 |
| others[3] |
2080 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T120 |
1 |
| false |
633 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T128 |
1 |
| true |
436 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T2 |
1 |
|
T22 |
2 |
|
T56 |
2 |
| others[1] |
94 |
1 |
|
T22 |
4 |
|
T56 |
3 |
|
T95 |
3 |
| others[2] |
101 |
1 |
|
T2 |
1 |
|
T22 |
7 |
|
T56 |
4 |
| others[3] |
174 |
1 |
|
T28 |
1 |
|
T22 |
2 |
|
T56 |
5 |
| false |
55 |
1 |
|
T3 |
1 |
|
T22 |
4 |
|
T56 |
4 |
| true |
6332 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T19 |
1 |
|
T28 |
1 |
|
T22 |
10 |
| others[1] |
239 |
1 |
|
T2 |
1 |
|
T19 |
3 |
|
T22 |
11 |
| others[2] |
226 |
1 |
|
T28 |
1 |
|
T22 |
7 |
|
T56 |
10 |
| others[3] |
394 |
1 |
|
T2 |
1 |
|
T19 |
2 |
|
T20 |
1 |
| false |
132 |
1 |
|
T22 |
4 |
|
T41 |
1 |
|
T56 |
7 |
| true |
5652 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1027 |
1 |
|
T203 |
1 |
|
T307 |
1 |
|
T339 |
1 |
| others[1] |
1025 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| others[2] |
1041 |
1 |
|
T119 |
1 |
|
T334 |
1 |
|
T306 |
1 |
| others[3] |
1834 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T129 |
1 |
| false |
541 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T117 |
1 |
| true |
1390 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T28 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T2 |
1 |
|
T19 |
2 |
|
T24 |
1 |
| others[1] |
204 |
1 |
|
T8 |
1 |
|
T28 |
1 |
|
T22 |
7 |
| others[2] |
204 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T22 |
10 |
| others[3] |
400 |
1 |
|
T3 |
1 |
|
T19 |
2 |
|
T28 |
1 |
| false |
125 |
1 |
|
T19 |
1 |
|
T22 |
5 |
|
T56 |
3 |
| true |
5672 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T2 |
1 |
|
T22 |
3 |
|
T56 |
12 |
| others[1] |
205 |
1 |
|
T28 |
1 |
|
T22 |
9 |
|
T56 |
8 |
| others[2] |
230 |
1 |
|
T22 |
13 |
|
T56 |
8 |
|
T52 |
1 |
| others[3] |
345 |
1 |
|
T8 |
1 |
|
T28 |
3 |
|
T22 |
17 |
| false |
105 |
1 |
|
T22 |
3 |
|
T56 |
3 |
|
T95 |
5 |
| true |
5766 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T120 |
1 |
|
T308 |
1 |
|
T337 |
1 |
| others[1] |
1212 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T111 |
1 |
| others[2] |
1237 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T203 |
1 |
| others[3] |
2054 |
1 |
|
T46 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| false |
646 |
1 |
|
T123 |
1 |
|
T127 |
1 |
|
T22 |
6 |
| true |
448 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T50 |
1 |
|
T117 |
1 |
|
T341 |
1 |
| others[1] |
1155 |
1 |
|
T119 |
1 |
|
T254 |
1 |
|
T337 |
1 |
| others[2] |
1244 |
1 |
|
T49 |
1 |
|
T203 |
1 |
|
T114 |
1 |
| others[3] |
2072 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| false |
691 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T131 |
1 |
| true |
421 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T22 |
3 |
|
T56 |
3 |
|
T95 |
3 |
| others[1] |
131 |
1 |
|
T1 |
1 |
|
T22 |
4 |
|
T95 |
3 |
| others[2] |
99 |
1 |
|
T2 |
1 |
|
T22 |
6 |
|
T56 |
5 |
| others[3] |
184 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
2 |
| false |
48 |
1 |
|
T22 |
2 |
|
T56 |
1 |
|
T345 |
1 |
| true |
6304 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T19 |
1 |
|
T22 |
10 |
|
T56 |
8 |
| others[1] |
255 |
1 |
|
T19 |
1 |
|
T28 |
1 |
|
T22 |
10 |
| others[2] |
207 |
1 |
|
T22 |
8 |
|
T56 |
4 |
|
T95 |
9 |
| others[3] |
424 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
118 |
1 |
|
T19 |
1 |
|
T22 |
2 |
|
T56 |
3 |
| true |
5613 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1023 |
1 |
|
T119 |
1 |
|
T128 |
1 |
|
T308 |
1 |
| others[1] |
1081 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T120 |
1 |
| others[2] |
1066 |
1 |
|
T49 |
1 |
|
T203 |
1 |
|
T123 |
1 |
| others[3] |
1785 |
1 |
|
T50 |
1 |
|
T111 |
1 |
|
T129 |
1 |
| false |
571 |
1 |
|
T334 |
1 |
|
T127 |
1 |
|
T2 |
1 |
| true |
1332 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T28 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T28 |
1 |
|
T22 |
14 |
|
T56 |
5 |
| others[1] |
275 |
1 |
|
T8 |
1 |
|
T28 |
2 |
|
T22 |
13 |
| others[2] |
219 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T22 |
8 |
| others[3] |
349 |
1 |
|
T28 |
1 |
|
T22 |
14 |
|
T56 |
19 |
| false |
129 |
1 |
|
T24 |
1 |
|
T22 |
6 |
|
T56 |
8 |
| true |
5649 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T22 |
7 |
|
T56 |
9 |
|
T95 |
4 |
| others[1] |
219 |
1 |
|
T22 |
8 |
|
T56 |
11 |
|
T95 |
10 |
| others[2] |
213 |
1 |
|
T22 |
13 |
|
T56 |
7 |
|
T95 |
12 |
| others[3] |
363 |
1 |
|
T8 |
1 |
|
T28 |
1 |
|
T22 |
14 |
| false |
126 |
1 |
|
T20 |
1 |
|
T22 |
5 |
|
T56 |
5 |
| true |
5721 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1183 |
1 |
|
T48 |
1 |
|
T123 |
1 |
|
T336 |
1 |
| others[1] |
1261 |
1 |
|
T49 |
1 |
|
T113 |
1 |
|
T204 |
1 |
| others[2] |
1269 |
1 |
|
T46 |
1 |
|
T129 |
1 |
|
T114 |
1 |
| others[3] |
2081 |
1 |
|
T120 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| false |
637 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T203 |
1 |
| true |
427 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T49 |
1 |
|
T22 |
21 |
|
T25 |
1 |
| others[1] |
1252 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T308 |
1 |
| others[2] |
1284 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T117 |
1 |
| others[3] |
1993 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| false |
684 |
1 |
|
T334 |
1 |
|
T307 |
1 |
|
T335 |
1 |
| true |
420 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T2 |
1 |
|
T22 |
5 |
|
T56 |
5 |
| others[1] |
130 |
1 |
|
T22 |
3 |
|
T56 |
1 |
|
T95 |
7 |
| others[2] |
105 |
1 |
|
T22 |
6 |
|
T56 |
1 |
|
T95 |
4 |
| others[3] |
152 |
1 |
|
T28 |
1 |
|
T22 |
1 |
|
T56 |
8 |
| false |
46 |
1 |
|
T2 |
1 |
|
T56 |
2 |
|
T95 |
2 |
| true |
6325 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T19 |
1 |
|
T22 |
3 |
|
T51 |
1 |
| others[1] |
239 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T28 |
1 |
| others[2] |
237 |
1 |
|
T28 |
1 |
|
T22 |
13 |
|
T56 |
13 |
| others[3] |
415 |
1 |
|
T19 |
4 |
|
T8 |
1 |
|
T28 |
1 |
| false |
114 |
1 |
|
T22 |
2 |
|
T56 |
4 |
|
T57 |
1 |
| true |
5630 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1031 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T307 |
1 |
| others[1] |
1076 |
1 |
|
T111 |
1 |
|
T131 |
1 |
|
T113 |
1 |
| others[2] |
1005 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T128 |
1 |
| others[3] |
1711 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T129 |
1 |
| false |
558 |
1 |
|
T340 |
1 |
|
T126 |
1 |
|
T22 |
10 |
| true |
1477 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T22 |
18 |
|
T56 |
7 |
|
T95 |
7 |
| others[1] |
245 |
1 |
|
T3 |
1 |
|
T28 |
2 |
|
T22 |
9 |
| others[2] |
236 |
1 |
|
T22 |
9 |
|
T73 |
1 |
|
T56 |
7 |
| others[3] |
412 |
1 |
|
T1 |
1 |
|
T28 |
1 |
|
T22 |
14 |
| false |
111 |
1 |
|
T2 |
1 |
|
T22 |
3 |
|
T56 |
3 |
| true |
5630 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T28 |
1 |
|
T22 |
10 |
|
T56 |
6 |
| others[1] |
223 |
1 |
|
T28 |
1 |
|
T22 |
7 |
|
T56 |
13 |
| others[2] |
199 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
6 |
| others[3] |
393 |
1 |
|
T22 |
10 |
|
T56 |
16 |
|
T95 |
19 |
| false |
104 |
1 |
|
T22 |
10 |
|
T56 |
3 |
|
T176 |
1 |
| true |
5714 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T50 |
1 |
|
T308 |
1 |
|
T204 |
1 |
| others[1] |
1198 |
1 |
|
T337 |
1 |
|
T332 |
1 |
|
T339 |
1 |
| others[2] |
1244 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T120 |
1 |
| others[3] |
2078 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T128 |
1 |
| false |
685 |
1 |
|
T111 |
1 |
|
T335 |
1 |
|
T22 |
14 |
| true |
441 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T119 |
1 |
|
T308 |
1 |
|
T336 |
1 |
| others[1] |
1263 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T120 |
1 |
| others[2] |
1213 |
1 |
|
T48 |
1 |
|
T131 |
1 |
|
T254 |
1 |
| others[3] |
2121 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T129 |
1 |
| false |
596 |
1 |
|
T123 |
1 |
|
T2 |
1 |
|
T22 |
8 |
| true |
429 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T22 |
5 |
|
T56 |
8 |
|
T95 |
6 |
| others[1] |
95 |
1 |
|
T2 |
1 |
|
T56 |
3 |
|
T52 |
1 |
| others[2] |
116 |
1 |
|
T28 |
1 |
|
T22 |
4 |
|
T56 |
3 |
| others[3] |
166 |
1 |
|
T2 |
1 |
|
T22 |
14 |
|
T56 |
7 |
| false |
61 |
1 |
|
T22 |
3 |
|
T95 |
4 |
|
T178 |
1 |
| true |
6304 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T28 |
1 |
| others[1] |
237 |
1 |
|
T1 |
1 |
|
T22 |
15 |
|
T56 |
8 |
| others[2] |
248 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
9 |
| others[3] |
426 |
1 |
|
T8 |
1 |
|
T28 |
1 |
|
T22 |
20 |
| false |
98 |
1 |
|
T22 |
4 |
|
T51 |
1 |
|
T56 |
8 |
| true |
5615 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T204 |
1 |
| others[1] |
1008 |
1 |
|
T120 |
1 |
|
T308 |
1 |
|
T337 |
1 |
| others[2] |
1111 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T50 |
1 |
| others[3] |
1751 |
1 |
|
T131 |
1 |
|
T203 |
1 |
|
T113 |
1 |
| false |
549 |
1 |
|
T119 |
1 |
|
T123 |
1 |
|
T2 |
1 |
| true |
1374 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |