Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T1 |
1 |
|
T22 |
9 |
|
T56 |
6 |
| others[1] |
223 |
1 |
|
T20 |
1 |
|
T8 |
1 |
|
T22 |
8 |
| others[2] |
241 |
1 |
|
T22 |
11 |
|
T73 |
1 |
|
T56 |
6 |
| others[3] |
343 |
1 |
|
T22 |
11 |
|
T56 |
14 |
|
T95 |
20 |
| false |
111 |
1 |
|
T22 |
4 |
|
T56 |
5 |
|
T95 |
6 |
| true |
5697 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T28 |
1 |
|
T22 |
5 |
|
T73 |
1 |
| others[1] |
192 |
1 |
|
T8 |
1 |
|
T22 |
6 |
|
T56 |
9 |
| others[2] |
213 |
1 |
|
T1 |
1 |
|
T22 |
5 |
|
T56 |
5 |
| others[3] |
390 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T28 |
1 |
| false |
124 |
1 |
|
T28 |
1 |
|
T22 |
6 |
|
T56 |
7 |
| true |
5738 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T46 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| others[1] |
1168 |
1 |
|
T48 |
1 |
|
T203 |
1 |
|
T337 |
1 |
| others[2] |
1267 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T254 |
1 |
| others[3] |
2100 |
1 |
|
T131 |
1 |
|
T113 |
1 |
|
T204 |
1 |
| false |
622 |
1 |
|
T50 |
1 |
|
T308 |
1 |
|
T334 |
1 |
| true |
449 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T128 |
1 |
|
T203 |
1 |
|
T254 |
1 |
| others[1] |
1219 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T120 |
1 |
| others[2] |
1250 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T129 |
1 |
| others[3] |
2088 |
1 |
|
T111 |
1 |
|
T131 |
1 |
|
T113 |
1 |
| false |
631 |
1 |
|
T119 |
1 |
|
T22 |
13 |
|
T25 |
2 |
| true |
420 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T2 |
2 |
|
T22 |
4 |
|
T56 |
6 |
| others[1] |
84 |
1 |
|
T22 |
2 |
|
T56 |
7 |
|
T95 |
2 |
| others[2] |
103 |
1 |
|
T22 |
3 |
|
T56 |
2 |
|
T95 |
5 |
| others[3] |
175 |
1 |
|
T22 |
2 |
|
T56 |
9 |
|
T95 |
5 |
| false |
45 |
1 |
|
T22 |
3 |
|
T56 |
3 |
|
T95 |
2 |
| true |
6339 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T20 |
1 |
|
T56 |
11 |
|
T95 |
7 |
| others[1] |
246 |
1 |
|
T2 |
1 |
|
T22 |
15 |
|
T33 |
1 |
| others[2] |
221 |
1 |
|
T22 |
12 |
|
T56 |
8 |
|
T95 |
7 |
| others[3] |
399 |
1 |
|
T28 |
2 |
|
T22 |
17 |
|
T56 |
17 |
| false |
123 |
1 |
|
T22 |
3 |
|
T56 |
5 |
|
T95 |
6 |
| true |
5625 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T119 |
1 |
|
T111 |
1 |
|
T129 |
1 |
| others[1] |
1064 |
1 |
|
T50 |
1 |
|
T128 |
1 |
|
T203 |
1 |
| others[2] |
1062 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T254 |
1 |
| others[3] |
1789 |
1 |
|
T46 |
1 |
|
T120 |
1 |
|
T337 |
1 |
| false |
533 |
1 |
|
T126 |
1 |
|
T2 |
1 |
|
T22 |
10 |
| true |
1345 |
1 |
|
T20 |
1 |
|
T28 |
5 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T28 |
1 |
|
T24 |
1 |
|
T22 |
10 |
| others[1] |
213 |
1 |
|
T1 |
1 |
|
T22 |
10 |
|
T56 |
14 |
| others[2] |
204 |
1 |
|
T8 |
1 |
|
T28 |
1 |
|
T22 |
13 |
| others[3] |
407 |
1 |
|
T28 |
2 |
|
T22 |
23 |
|
T56 |
17 |
| false |
113 |
1 |
|
T56 |
1 |
|
T58 |
1 |
|
T95 |
10 |
| true |
5686 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T22 |
9 |
|
T56 |
8 |
|
T176 |
1 |
| others[1] |
218 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T22 |
12 |
| others[2] |
233 |
1 |
|
T22 |
9 |
|
T56 |
9 |
|
T95 |
9 |
| others[3] |
355 |
1 |
|
T8 |
1 |
|
T28 |
3 |
|
T22 |
14 |
| false |
123 |
1 |
|
T22 |
5 |
|
T56 |
8 |
|
T95 |
6 |
| true |
5704 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T119 |
1 |
|
T120 |
1 |
|
T254 |
1 |
| others[1] |
1218 |
1 |
|
T129 |
1 |
|
T131 |
1 |
|
T113 |
1 |
| others[2] |
1284 |
1 |
|
T48 |
1 |
|
T117 |
1 |
|
T341 |
1 |
| others[3] |
2016 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T128 |
1 |
| false |
634 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T204 |
1 |
| true |
447 |
1 |
|
T1 |
1 |
|
T19 |
5 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T48 |
1 |
|
T111 |
1 |
|
T203 |
1 |
| others[1] |
1271 |
1 |
|
T204 |
1 |
|
T335 |
1 |
|
T2 |
2 |
| others[2] |
1237 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| others[3] |
2127 |
1 |
|
T49 |
1 |
|
T128 |
1 |
|
T131 |
1 |
| false |
603 |
1 |
|
T46 |
1 |
|
T334 |
1 |
|
T306 |
1 |
| true |
425 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T8 |
1 |
|
T22 |
1 |
|
T56 |
4 |
| others[1] |
107 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T22 |
4 |
| others[2] |
90 |
1 |
|
T2 |
1 |
|
T22 |
5 |
|
T56 |
4 |
| others[3] |
164 |
1 |
|
T22 |
8 |
|
T56 |
9 |
|
T52 |
1 |
| false |
50 |
1 |
|
T22 |
1 |
|
T95 |
4 |
|
T333 |
1 |
| true |
6348 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
195 |
1 |
|
T20 |
1 |
|
T8 |
1 |
|
T22 |
5 |
| others[1] |
229 |
1 |
|
T28 |
1 |
|
T22 |
11 |
|
T56 |
5 |
| others[2] |
214 |
1 |
|
T1 |
1 |
|
T22 |
7 |
|
T41 |
1 |
| others[3] |
420 |
1 |
|
T3 |
1 |
|
T28 |
1 |
|
T22 |
21 |
| false |
134 |
1 |
|
T22 |
5 |
|
T56 |
7 |
|
T95 |
5 |
| true |
5666 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1036 |
1 |
|
T49 |
1 |
|
T204 |
1 |
|
T337 |
1 |
| others[1] |
1115 |
1 |
|
T111 |
1 |
|
T128 |
1 |
|
T114 |
1 |
| others[2] |
1071 |
1 |
|
T203 |
1 |
|
T335 |
1 |
|
T341 |
1 |
| others[3] |
1748 |
1 |
|
T119 |
1 |
|
T129 |
1 |
|
T131 |
1 |
| false |
547 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T50 |
1 |
| true |
1341 |
1 |
|
T19 |
6 |
|
T28 |
3 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T3 |
1 |
|
T28 |
1 |
|
T22 |
9 |
| others[1] |
218 |
1 |
|
T20 |
1 |
|
T22 |
7 |
|
T56 |
7 |
| others[2] |
223 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
9 |
| others[3] |
406 |
1 |
|
T28 |
1 |
|
T22 |
16 |
|
T56 |
20 |
| false |
113 |
1 |
|
T22 |
2 |
|
T56 |
5 |
|
T95 |
8 |
| true |
5649 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T28 |
1 |
|
T22 |
6 |
|
T56 |
6 |
| others[1] |
217 |
1 |
|
T2 |
1 |
|
T22 |
11 |
|
T56 |
7 |
| others[2] |
218 |
1 |
|
T28 |
1 |
|
T22 |
8 |
|
T56 |
7 |
| others[3] |
346 |
1 |
|
T22 |
18 |
|
T56 |
18 |
|
T95 |
18 |
| false |
125 |
1 |
|
T2 |
1 |
|
T22 |
5 |
|
T56 |
3 |
| true |
5753 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T131 |
1 |
| others[1] |
1234 |
1 |
|
T119 |
1 |
|
T254 |
1 |
|
T306 |
1 |
| others[2] |
1237 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T111 |
1 |
| others[3] |
2056 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T129 |
1 |
| false |
666 |
1 |
|
T203 |
1 |
|
T307 |
1 |
|
T341 |
1 |
| true |
452 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| others[1] |
1207 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T129 |
1 |
| others[2] |
1228 |
1 |
|
T49 |
1 |
|
T131 |
1 |
|
T117 |
1 |
| others[3] |
2124 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T254 |
1 |
| false |
635 |
1 |
|
T334 |
1 |
|
T123 |
1 |
|
T21 |
1 |
| true |
437 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T1 |
1 |
|
T28 |
1 |
|
T22 |
2 |
| others[1] |
117 |
1 |
|
T2 |
1 |
|
T22 |
4 |
|
T56 |
5 |
| others[2] |
102 |
1 |
|
T22 |
4 |
|
T56 |
4 |
|
T95 |
6 |
| others[3] |
171 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
2 |
| false |
52 |
1 |
|
T22 |
1 |
|
T56 |
4 |
|
T95 |
1 |
| true |
6315 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T3 |
1 |
|
T22 |
13 |
|
T56 |
11 |
| others[1] |
198 |
1 |
|
T1 |
1 |
|
T19 |
2 |
|
T28 |
2 |
| others[2] |
232 |
1 |
|
T19 |
2 |
|
T28 |
1 |
|
T22 |
7 |
| others[3] |
376 |
1 |
|
T19 |
1 |
|
T22 |
14 |
|
T56 |
15 |
| false |
123 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T22 |
2 |
| true |
5714 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T120 |
1 |
| others[1] |
1063 |
1 |
|
T119 |
1 |
|
T111 |
1 |
|
T129 |
1 |
| others[2] |
1068 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T307 |
1 |
| others[3] |
1733 |
1 |
|
T128 |
1 |
|
T113 |
1 |
|
T114 |
1 |
| false |
532 |
1 |
|
T335 |
1 |
|
T340 |
1 |
|
T2 |
1 |
| true |
1403 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T19 |
1 |
|
T28 |
1 |
|
T22 |
14 |
| others[1] |
231 |
1 |
|
T19 |
2 |
|
T24 |
1 |
|
T22 |
11 |
| others[2] |
249 |
1 |
|
T19 |
2 |
|
T28 |
1 |
|
T22 |
8 |
| others[3] |
387 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| false |
122 |
1 |
|
T22 |
8 |
|
T56 |
6 |
|
T95 |
6 |
| true |
5649 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T28 |
1 |
|
T22 |
11 |
|
T33 |
1 |
| others[1] |
211 |
1 |
|
T2 |
2 |
|
T22 |
15 |
|
T73 |
1 |
| others[2] |
240 |
1 |
|
T1 |
1 |
|
T22 |
10 |
|
T56 |
15 |
| others[3] |
371 |
1 |
|
T3 |
1 |
|
T28 |
2 |
|
T22 |
10 |
| false |
128 |
1 |
|
T28 |
1 |
|
T22 |
10 |
|
T56 |
6 |
| true |
5664 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T204 |
1 |
| others[1] |
1177 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T117 |
1 |
| others[2] |
1303 |
1 |
|
T119 |
1 |
|
T129 |
1 |
|
T131 |
1 |
| others[3] |
2066 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| false |
659 |
1 |
|
T113 |
1 |
|
T22 |
11 |
|
T25 |
2 |
| true |
447 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1194 |
1 |
|
T46 |
1 |
|
T120 |
1 |
|
T334 |
1 |
| others[1] |
1221 |
1 |
|
T50 |
1 |
|
T111 |
1 |
|
T308 |
1 |
| others[2] |
1237 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T131 |
1 |
| others[3] |
2091 |
1 |
|
T119 |
1 |
|
T129 |
1 |
|
T113 |
1 |
| false |
689 |
1 |
|
T128 |
1 |
|
T332 |
1 |
|
T335 |
1 |
| true |
426 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T22 |
7 |
|
T33 |
1 |
|
T56 |
1 |
| others[1] |
102 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
6 |
| others[2] |
118 |
1 |
|
T22 |
3 |
|
T56 |
7 |
|
T95 |
5 |
| others[3] |
154 |
1 |
|
T22 |
5 |
|
T56 |
5 |
|
T52 |
1 |
| false |
53 |
1 |
|
T2 |
1 |
|
T95 |
1 |
|
T343 |
1 |
| true |
6323 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T8 |
1 |
|
T22 |
8 |
|
T56 |
9 |
| others[1] |
236 |
1 |
|
T28 |
1 |
|
T22 |
10 |
|
T56 |
13 |
| others[2] |
206 |
1 |
|
T28 |
2 |
|
T22 |
8 |
|
T56 |
11 |
| others[3] |
392 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
123 |
1 |
|
T22 |
4 |
|
T56 |
5 |
|
T95 |
8 |
| true |
5651 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T254 |
1 |
|
T308 |
1 |
|
T336 |
1 |
| others[1] |
1066 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T129 |
1 |
| others[2] |
1046 |
1 |
|
T131 |
1 |
|
T203 |
1 |
|
T113 |
1 |
| others[3] |
1725 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
554 |
1 |
|
T49 |
1 |
|
T117 |
1 |
|
T306 |
1 |
| true |
1425 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T22 |
9 |
|
T56 |
10 |
|
T176 |
1 |
| others[1] |
233 |
1 |
|
T8 |
1 |
|
T22 |
6 |
|
T51 |
1 |
| others[2] |
249 |
1 |
|
T1 |
1 |
|
T28 |
2 |
|
T24 |
1 |
| others[3] |
378 |
1 |
|
T3 |
1 |
|
T22 |
18 |
|
T33 |
1 |
| false |
109 |
1 |
|
T28 |
1 |
|
T22 |
7 |
|
T56 |
8 |
| true |
5671 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T22 |
15 |
| others[1] |
213 |
1 |
|
T2 |
1 |
|
T22 |
12 |
|
T56 |
5 |
| others[2] |
219 |
1 |
|
T28 |
2 |
|
T22 |
9 |
|
T73 |
1 |
| others[3] |
351 |
1 |
|
T22 |
14 |
|
T56 |
11 |
|
T176 |
1 |
| false |
103 |
1 |
|
T22 |
3 |
|
T56 |
1 |
|
T95 |
4 |
| true |
5724 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T128 |
1 |
|
T204 |
1 |
|
T117 |
1 |
| others[1] |
1197 |
1 |
|
T49 |
1 |
|
T113 |
1 |
|
T339 |
1 |
| others[2] |
1251 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| others[3] |
2048 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
698 |
1 |
|
T114 |
1 |
|
T308 |
1 |
|
T337 |
1 |
| true |
435 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |