Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T120 |
1 |
|
T308 |
1 |
|
T335 |
1 |
| others[1] |
1235 |
1 |
|
T111 |
1 |
|
T129 |
1 |
|
T337 |
1 |
| others[2] |
1260 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T119 |
1 |
| others[3] |
2077 |
1 |
|
T49 |
1 |
|
T113 |
1 |
|
T114 |
1 |
| false |
616 |
1 |
|
T50 |
1 |
|
T128 |
1 |
|
T131 |
1 |
| true |
421 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T22 |
1 |
|
T56 |
5 |
|
T176 |
1 |
| others[1] |
100 |
1 |
|
T22 |
5 |
|
T95 |
3 |
|
T235 |
1 |
| others[2] |
97 |
1 |
|
T2 |
1 |
|
T22 |
2 |
|
T56 |
1 |
| others[3] |
154 |
1 |
|
T2 |
1 |
|
T22 |
6 |
|
T56 |
10 |
| false |
61 |
1 |
|
T22 |
3 |
|
T56 |
4 |
|
T95 |
2 |
| true |
6347 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T28 |
1 |
|
T22 |
6 |
|
T56 |
15 |
| others[1] |
255 |
1 |
|
T22 |
8 |
|
T56 |
11 |
|
T95 |
7 |
| others[2] |
250 |
1 |
|
T28 |
1 |
|
T22 |
14 |
|
T56 |
11 |
| others[3] |
395 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T22 |
16 |
| false |
116 |
1 |
|
T28 |
1 |
|
T22 |
4 |
|
T56 |
6 |
| true |
5601 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
961 |
1 |
|
T129 |
1 |
|
T334 |
1 |
|
T332 |
1 |
| others[1] |
1068 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T111 |
1 |
| others[2] |
1072 |
1 |
|
T203 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| others[3] |
1767 |
1 |
|
T46 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| false |
568 |
1 |
|
T50 |
1 |
|
T335 |
1 |
|
T126 |
1 |
| true |
1422 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
7 |
| others[1] |
207 |
1 |
|
T22 |
8 |
|
T56 |
8 |
|
T95 |
6 |
| others[2] |
236 |
1 |
|
T28 |
1 |
|
T24 |
1 |
|
T22 |
11 |
| others[3] |
399 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T8 |
1 |
| false |
122 |
1 |
|
T22 |
7 |
|
T56 |
2 |
|
T95 |
6 |
| true |
5668 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T22 |
6 |
|
T56 |
15 |
|
T95 |
13 |
| others[1] |
243 |
1 |
|
T22 |
8 |
|
T33 |
1 |
|
T56 |
5 |
| others[2] |
213 |
1 |
|
T20 |
1 |
|
T22 |
11 |
|
T56 |
11 |
| others[3] |
353 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
102 |
1 |
|
T22 |
7 |
|
T56 |
4 |
|
T95 |
3 |
| true |
5700 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T114 |
1 |
| others[1] |
1281 |
1 |
|
T119 |
1 |
|
T128 |
1 |
|
T131 |
1 |
| others[2] |
1230 |
1 |
|
T120 |
1 |
|
T306 |
1 |
|
T340 |
1 |
| others[3] |
2041 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T129 |
1 |
| false |
637 |
1 |
|
T111 |
1 |
|
T341 |
1 |
|
T22 |
11 |
| true |
442 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T113 |
1 |
| others[1] |
1256 |
1 |
|
T114 |
1 |
|
T307 |
1 |
|
T335 |
1 |
| others[2] |
1259 |
1 |
|
T49 |
1 |
|
T128 |
1 |
|
T129 |
1 |
| others[3] |
2042 |
1 |
|
T119 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| false |
602 |
1 |
|
T50 |
1 |
|
T203 |
1 |
|
T332 |
1 |
| true |
435 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
111 |
1 |
|
T22 |
5 |
|
T56 |
3 |
|
T95 |
4 |
| others[1] |
95 |
1 |
|
T22 |
3 |
|
T56 |
5 |
|
T95 |
4 |
| others[2] |
120 |
1 |
|
T2 |
2 |
|
T22 |
2 |
|
T56 |
3 |
| others[3] |
161 |
1 |
|
T22 |
12 |
|
T56 |
9 |
|
T95 |
8 |
| false |
55 |
1 |
|
T22 |
1 |
|
T56 |
4 |
|
T95 |
3 |
| true |
6316 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T19 |
1 |
|
T22 |
9 |
|
T33 |
1 |
| others[1] |
229 |
1 |
|
T20 |
1 |
|
T22 |
11 |
|
T41 |
1 |
| others[2] |
238 |
1 |
|
T2 |
1 |
|
T19 |
3 |
|
T28 |
1 |
| others[3] |
385 |
1 |
|
T2 |
1 |
|
T19 |
2 |
|
T28 |
1 |
| false |
126 |
1 |
|
T24 |
1 |
|
T22 |
2 |
|
T56 |
12 |
| true |
5640 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1020 |
1 |
|
T129 |
1 |
|
T113 |
1 |
|
T308 |
1 |
| others[1] |
968 |
1 |
|
T50 |
1 |
|
T203 |
1 |
|
T114 |
1 |
| others[2] |
1082 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T254 |
1 |
| others[3] |
1798 |
1 |
|
T49 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| false |
565 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T28 |
1 |
| true |
1425 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T19 |
1 |
|
T28 |
2 |
|
T22 |
9 |
| others[1] |
226 |
1 |
|
T19 |
1 |
|
T22 |
10 |
|
T56 |
11 |
| others[2] |
227 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T22 |
7 |
| others[3] |
386 |
1 |
|
T19 |
3 |
|
T28 |
2 |
|
T22 |
29 |
| false |
121 |
1 |
|
T22 |
3 |
|
T56 |
9 |
|
T95 |
8 |
| true |
5674 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T22 |
7 |
|
T56 |
5 |
|
T95 |
3 |
| others[1] |
242 |
1 |
|
T22 |
20 |
|
T56 |
10 |
|
T95 |
12 |
| others[2] |
213 |
1 |
|
T28 |
1 |
|
T22 |
6 |
|
T33 |
1 |
| others[3] |
391 |
1 |
|
T2 |
1 |
|
T22 |
17 |
|
T56 |
15 |
| false |
88 |
1 |
|
T22 |
3 |
|
T56 |
5 |
|
T95 |
4 |
| true |
5717 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T128 |
1 |
| others[1] |
1265 |
1 |
|
T119 |
1 |
|
T120 |
1 |
|
T113 |
1 |
| others[2] |
1232 |
1 |
|
T129 |
1 |
|
T203 |
1 |
|
T337 |
1 |
| others[3] |
2075 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T308 |
1 |
| false |
616 |
1 |
|
T48 |
1 |
|
T254 |
1 |
|
T22 |
11 |
| true |
443 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| others[1] |
1193 |
1 |
|
T49 |
1 |
|
T113 |
1 |
|
T254 |
1 |
| others[2] |
1213 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T335 |
1 |
| others[3] |
2142 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T203 |
1 |
| false |
629 |
1 |
|
T204 |
1 |
|
T22 |
13 |
|
T56 |
9 |
| true |
422 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T56 |
3 |
| others[1] |
107 |
1 |
|
T22 |
5 |
|
T56 |
5 |
|
T95 |
3 |
| others[2] |
108 |
1 |
|
T2 |
1 |
|
T28 |
1 |
|
T22 |
6 |
| others[3] |
207 |
1 |
|
T8 |
1 |
|
T22 |
4 |
|
T56 |
6 |
| false |
44 |
1 |
|
T56 |
2 |
|
T83 |
1 |
|
T333 |
1 |
| true |
6282 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T19 |
1 |
|
T22 |
10 |
|
T51 |
1 |
| others[1] |
226 |
1 |
|
T24 |
1 |
|
T22 |
10 |
|
T56 |
12 |
| others[2] |
258 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T19 |
1 |
| others[3] |
392 |
1 |
|
T19 |
3 |
|
T20 |
1 |
|
T28 |
3 |
| false |
118 |
1 |
|
T19 |
1 |
|
T28 |
1 |
|
T22 |
3 |
| true |
5629 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T49 |
1 |
|
T114 |
1 |
|
T337 |
1 |
| others[1] |
1040 |
1 |
|
T204 |
1 |
|
T306 |
1 |
|
T332 |
1 |
| others[2] |
1032 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T129 |
1 |
| others[3] |
1757 |
1 |
|
T119 |
1 |
|
T120 |
1 |
|
T203 |
1 |
| false |
552 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T128 |
1 |
| true |
1387 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T20 |
1 |
|
T22 |
7 |
|
T56 |
10 |
| others[1] |
245 |
1 |
|
T22 |
13 |
|
T51 |
1 |
|
T56 |
9 |
| others[2] |
230 |
1 |
|
T22 |
5 |
|
T56 |
11 |
|
T95 |
12 |
| others[3] |
422 |
1 |
|
T8 |
1 |
|
T28 |
1 |
|
T22 |
20 |
| false |
105 |
1 |
|
T22 |
5 |
|
T56 |
4 |
|
T95 |
1 |
| true |
5654 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T1 |
1 |
|
T22 |
10 |
|
T33 |
1 |
| others[1] |
216 |
1 |
|
T22 |
12 |
|
T56 |
16 |
|
T95 |
8 |
| others[2] |
220 |
1 |
|
T28 |
1 |
|
T22 |
16 |
|
T56 |
5 |
| others[3] |
368 |
1 |
|
T2 |
1 |
|
T28 |
2 |
|
T22 |
18 |
| false |
102 |
1 |
|
T22 |
2 |
|
T56 |
5 |
|
T95 |
4 |
| true |
5728 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T129 |
1 |
| others[1] |
1214 |
1 |
|
T203 |
1 |
|
T117 |
1 |
|
T332 |
1 |
| others[2] |
1263 |
1 |
|
T111 |
1 |
|
T128 |
1 |
|
T254 |
1 |
| others[3] |
2060 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| false |
627 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T308 |
1 |
| true |
447 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1257 |
1 |
|
T111 |
1 |
|
T128 |
1 |
|
T113 |
1 |
| others[1] |
1265 |
1 |
|
T203 |
1 |
|
T337 |
1 |
|
T307 |
1 |
| others[2] |
1213 |
1 |
|
T49 |
1 |
|
T114 |
1 |
|
T335 |
1 |
| others[3] |
2082 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
613 |
1 |
|
T46 |
1 |
|
T120 |
1 |
|
T308 |
1 |
| true |
428 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
122 |
1 |
|
T22 |
5 |
|
T56 |
7 |
|
T95 |
2 |
| others[1] |
88 |
1 |
|
T28 |
1 |
|
T22 |
4 |
|
T56 |
3 |
| others[2] |
111 |
1 |
|
T8 |
1 |
|
T22 |
2 |
|
T56 |
6 |
| others[3] |
160 |
1 |
|
T2 |
2 |
|
T22 |
5 |
|
T56 |
4 |
| false |
56 |
1 |
|
T22 |
1 |
|
T56 |
1 |
|
T178 |
1 |
| true |
6321 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T3 |
1 |
|
T28 |
2 |
|
T22 |
8 |
| others[1] |
232 |
1 |
|
T20 |
1 |
|
T22 |
9 |
|
T56 |
9 |
| others[2] |
254 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
1 |
| others[3] |
420 |
1 |
|
T28 |
1 |
|
T22 |
18 |
|
T51 |
1 |
| false |
118 |
1 |
|
T22 |
5 |
|
T73 |
1 |
|
T56 |
7 |
| true |
5614 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T120 |
1 |
| others[1] |
1040 |
1 |
|
T128 |
1 |
|
T131 |
1 |
|
T254 |
1 |
| others[2] |
1095 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T111 |
1 |
| others[3] |
1771 |
1 |
|
T50 |
1 |
|
T203 |
1 |
|
T308 |
1 |
| false |
550 |
1 |
|
T332 |
1 |
|
T123 |
1 |
|
T336 |
1 |
| true |
1383 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T28 |
1 |
| others[1] |
213 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T8 |
1 |
| others[2] |
241 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| others[3] |
370 |
1 |
|
T19 |
3 |
|
T28 |
1 |
|
T22 |
19 |
| false |
133 |
1 |
|
T22 |
5 |
|
T56 |
3 |
|
T176 |
1 |
| true |
5691 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T22 |
7 |
|
T73 |
1 |
|
T56 |
8 |
| others[1] |
225 |
1 |
|
T8 |
1 |
|
T22 |
10 |
|
T56 |
15 |
| others[2] |
223 |
1 |
|
T22 |
7 |
|
T56 |
9 |
|
T95 |
8 |
| others[3] |
359 |
1 |
|
T28 |
1 |
|
T22 |
13 |
|
T56 |
14 |
| false |
107 |
1 |
|
T28 |
1 |
|
T22 |
4 |
|
T56 |
5 |
| true |
5747 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T119 |
1 |
|
T129 |
1 |
|
T341 |
1 |
| others[1] |
1286 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T204 |
1 |
| others[2] |
1205 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T123 |
1 |
| others[3] |
2074 |
1 |
|
T120 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| false |
622 |
1 |
|
T113 |
1 |
|
T337 |
1 |
|
T2 |
1 |
| true |
450 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T346 |
1 |
|
T347 |
1 |
|
T348 |
1 |
| others[1] |
15 |
1 |
|
T74 |
1 |
|
T155 |
1 |
|
T85 |
1 |
| others[2] |
5 |
1 |
|
T13 |
1 |
|
T165 |
1 |
|
T168 |
1 |
| others[3] |
13 |
1 |
|
T164 |
1 |
|
T167 |
1 |
|
T166 |
1 |
| false |
6 |
1 |
|
T349 |
1 |
|
T350 |
1 |
|
T351 |
1 |
| true |
57 |
1 |
|
T14 |
1 |
|
T133 |
1 |
|
T153 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T352 |
1 |
|
T353 |
1 |
|
T354 |
1 |
| others[1] |
3 |
1 |
|
T4 |
1 |
|
T355 |
1 |
|
T356 |
1 |
| others[2] |
1 |
1 |
|
T357 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
3 |
1 |
|
T358 |
1 |
|
T359 |
1 |
|
T360 |
1 |
| false |
11 |
1 |
|
T361 |
1 |
|
T362 |
1 |
|
T363 |
1 |
| true |
24 |
1 |
|
T27 |
1 |
|
T186 |
1 |
|
T328 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T363 |
1 |
|
T364 |
1 |
|
T365 |
1 |
| others[1] |
3 |
1 |
|
T186 |
1 |
|
T366 |
1 |
|
T367 |
1 |
| others[2] |
1 |
1 |
|
T355 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
5 |
1 |
|
T187 |
1 |
|
T368 |
1 |
|
T369 |
1 |
| false |
10 |
1 |
|
T4 |
1 |
|
T27 |
1 |
|
T328 |
1 |
| true |
23 |
1 |
|
T370 |
1 |
|
T371 |
1 |
|
T361 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |