Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9701 |
1 |
|
T119 |
1 |
|
T128 |
1 |
|
T203 |
1 |
| others[1] |
730 |
1 |
|
T46 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| others[2] |
820 |
1 |
|
T50 |
1 |
|
T254 |
1 |
|
T335 |
1 |
| others[3] |
1321 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T129 |
1 |
| false |
379 |
1 |
|
T308 |
1 |
|
T332 |
1 |
|
T19 |
1 |
| true |
521 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2289 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T203 |
1 |
| others[1] |
2317 |
1 |
|
T119 |
1 |
|
T111 |
1 |
|
T114 |
1 |
| others[2] |
2298 |
1 |
|
T129 |
1 |
|
T254 |
1 |
|
T308 |
1 |
| others[3] |
3785 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T131 |
1 |
| false |
1161 |
1 |
|
T49 |
1 |
|
T120 |
1 |
|
T28 |
1 |
| true |
1622 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9121 |
1 |
|
T114 |
1 |
|
T337 |
1 |
|
T340 |
1 |
| others[1] |
271 |
1 |
|
T128 |
1 |
|
T113 |
1 |
|
T308 |
1 |
| others[2] |
262 |
1 |
|
T111 |
1 |
|
T338 |
1 |
|
T342 |
1 |
| others[3] |
478 |
1 |
|
T46 |
1 |
|
T119 |
1 |
|
T334 |
1 |
| false |
140 |
1 |
|
T22 |
9 |
|
T25 |
1 |
|
T56 |
6 |
| true |
3200 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9327 |
1 |
|
T50 |
1 |
|
T111 |
1 |
|
T342 |
1 |
| others[1] |
440 |
1 |
|
T119 |
1 |
|
T306 |
1 |
|
T339 |
1 |
| others[2] |
495 |
1 |
|
T49 |
1 |
|
T204 |
1 |
|
T334 |
1 |
| others[3] |
766 |
1 |
|
T46 |
1 |
|
T120 |
1 |
|
T307 |
1 |
| false |
231 |
1 |
|
T117 |
1 |
|
T6 |
1 |
|
T22 |
4 |
| true |
2213 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T129 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9120 |
1 |
|
T119 |
1 |
|
T203 |
1 |
|
T114 |
1 |
| others[1] |
290 |
1 |
|
T128 |
1 |
|
T254 |
1 |
|
T307 |
1 |
| others[2] |
281 |
1 |
|
T337 |
1 |
|
T28 |
2 |
|
T22 |
10 |
| others[3] |
418 |
1 |
|
T49 |
1 |
|
T340 |
1 |
|
T341 |
1 |
| false |
116 |
1 |
|
T50 |
1 |
|
T113 |
1 |
|
T204 |
1 |
| true |
3247 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T120 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9084 |
1 |
|
T337 |
1 |
|
T334 |
1 |
|
T332 |
1 |
| others[1] |
232 |
1 |
|
T131 |
1 |
|
T248 |
1 |
|
T20 |
1 |
| others[2] |
268 |
1 |
|
T120 |
1 |
|
T340 |
1 |
|
T341 |
1 |
| others[3] |
443 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T119 |
1 |
| false |
119 |
1 |
|
T50 |
1 |
|
T28 |
1 |
|
T22 |
7 |
| true |
3326 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T128 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9647 |
1 |
|
T49 |
1 |
|
T131 |
1 |
|
T203 |
1 |
| others[1] |
791 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T254 |
1 |
| others[2] |
820 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| others[3] |
1308 |
1 |
|
T111 |
1 |
|
T129 |
1 |
|
T307 |
1 |
| false |
402 |
1 |
|
T204 |
1 |
|
T117 |
1 |
|
T340 |
1 |
| true |
504 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9627 |
1 |
|
T120 |
1 |
|
T128 |
1 |
|
T338 |
1 |
| others[1] |
820 |
1 |
|
T48 |
1 |
|
T111 |
1 |
|
T337 |
1 |
| others[2] |
783 |
1 |
|
T113 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| others[3] |
1288 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
388 |
1 |
|
T49 |
1 |
|
T117 |
1 |
|
T335 |
1 |
| true |
529 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2290 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T128 |
1 |
| others[1] |
2252 |
1 |
|
T113 |
1 |
|
T204 |
1 |
|
T117 |
1 |
| others[2] |
2342 |
1 |
|
T131 |
1 |
|
T306 |
1 |
|
T332 |
1 |
| others[3] |
3827 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
1184 |
1 |
|
T120 |
1 |
|
T21 |
1 |
|
T28 |
1 |
| true |
1540 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9093 |
1 |
|
T113 |
1 |
|
T306 |
1 |
|
T6 |
2 |
| others[1] |
280 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T127 |
1 |
| others[2] |
263 |
1 |
|
T119 |
1 |
|
T340 |
1 |
|
T339 |
1 |
| others[3] |
462 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T254 |
1 |
| false |
141 |
1 |
|
T128 |
1 |
|
T308 |
1 |
|
T2 |
1 |
| true |
3196 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T129 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9281 |
1 |
|
T120 |
1 |
|
T308 |
1 |
|
T332 |
1 |
| others[1] |
492 |
1 |
|
T254 |
1 |
|
T337 |
1 |
|
T2 |
1 |
| others[2] |
442 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T344 |
1 |
| others[3] |
746 |
1 |
|
T128 |
1 |
|
T129 |
1 |
|
T114 |
1 |
| false |
248 |
1 |
|
T338 |
1 |
|
T2 |
1 |
|
T22 |
8 |
| true |
2226 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9078 |
1 |
|
T129 |
1 |
|
T203 |
1 |
|
T337 |
1 |
| others[1] |
247 |
1 |
|
T48 |
1 |
|
T117 |
1 |
|
T332 |
1 |
| others[2] |
298 |
1 |
|
T120 |
1 |
|
T338 |
1 |
|
T126 |
1 |
| others[3] |
435 |
1 |
|
T306 |
1 |
|
T123 |
1 |
|
T339 |
1 |
| false |
146 |
1 |
|
T114 |
1 |
|
T19 |
1 |
|
T28 |
1 |
| true |
3231 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9085 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T117 |
1 |
| others[1] |
246 |
1 |
|
T46 |
1 |
|
T254 |
1 |
|
T308 |
1 |
| others[2] |
268 |
1 |
|
T204 |
1 |
|
T334 |
1 |
|
T338 |
1 |
| others[3] |
401 |
1 |
|
T203 |
1 |
|
T341 |
1 |
|
T127 |
1 |
| false |
145 |
1 |
|
T126 |
1 |
|
T22 |
6 |
|
T25 |
1 |
| true |
3290 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T120 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9652 |
1 |
|
T117 |
1 |
|
T332 |
1 |
|
T341 |
1 |
| others[1] |
734 |
1 |
|
T49 |
1 |
|
T129 |
1 |
|
T114 |
1 |
| others[2] |
808 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T203 |
1 |
| others[3] |
1349 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
383 |
1 |
|
T204 |
1 |
|
T334 |
1 |
|
T340 |
1 |
| true |
509 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9594 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T131 |
1 |
| others[1] |
771 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T111 |
1 |
| others[2] |
790 |
1 |
|
T308 |
1 |
|
T117 |
1 |
|
T306 |
1 |
| others[3] |
1334 |
1 |
|
T129 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| false |
413 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T113 |
1 |
| true |
533 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2353 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T117 |
1 |
| others[1] |
2199 |
1 |
|
T131 |
1 |
|
T113 |
1 |
|
T306 |
1 |
| others[2] |
2292 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T119 |
1 |
| others[3] |
3911 |
1 |
|
T50 |
1 |
|
T129 |
1 |
|
T203 |
1 |
| false |
1144 |
1 |
|
T120 |
1 |
|
T114 |
1 |
|
T337 |
1 |
| true |
1536 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9080 |
1 |
|
T3 |
1 |
|
T6 |
1 |
|
T21 |
1 |
| others[1] |
283 |
1 |
|
T128 |
1 |
|
T129 |
1 |
|
T131 |
1 |
| others[2] |
292 |
1 |
|
T46 |
1 |
|
T120 |
1 |
|
T114 |
1 |
| others[3] |
453 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
145 |
1 |
|
T332 |
1 |
|
T335 |
1 |
|
T22 |
7 |
| true |
3182 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T203 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9291 |
1 |
|
T120 |
1 |
|
T123 |
1 |
|
T338 |
1 |
| others[1] |
444 |
1 |
|
T119 |
1 |
|
T111 |
1 |
|
T117 |
1 |
| others[2] |
448 |
1 |
|
T128 |
1 |
|
T307 |
1 |
|
T332 |
1 |
| others[3] |
812 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T254 |
1 |
| false |
251 |
1 |
|
T48 |
1 |
|
T334 |
1 |
|
T6 |
1 |
| true |
2189 |
1 |
|
T46 |
1 |
|
T129 |
1 |
|
T131 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9064 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T3 |
1 |
| others[1] |
258 |
1 |
|
T119 |
1 |
|
T113 |
1 |
|
T335 |
1 |
| others[2] |
245 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T129 |
1 |
| others[3] |
437 |
1 |
|
T120 |
1 |
|
T131 |
1 |
|
T204 |
1 |
| false |
152 |
1 |
|
T344 |
1 |
|
T19 |
1 |
|
T28 |
1 |
| true |
3279 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T203 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9058 |
1 |
|
T307 |
1 |
|
T339 |
1 |
|
T344 |
1 |
| others[1] |
258 |
1 |
|
T50 |
1 |
|
T306 |
1 |
|
T248 |
1 |
| others[2] |
239 |
1 |
|
T114 |
1 |
|
T340 |
1 |
|
T2 |
1 |
| others[3] |
438 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T204 |
1 |
| false |
128 |
1 |
|
T254 |
1 |
|
T22 |
4 |
|
T56 |
10 |
| true |
3314 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T119 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9638 |
1 |
|
T308 |
1 |
|
T332 |
1 |
|
T335 |
1 |
| others[1] |
765 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T203 |
1 |
| others[2] |
805 |
1 |
|
T131 |
1 |
|
T204 |
1 |
|
T307 |
1 |
| others[3] |
1299 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| false |
423 |
1 |
|
T128 |
1 |
|
T334 |
1 |
|
T306 |
1 |
| true |
505 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9621 |
1 |
|
T117 |
1 |
|
T332 |
1 |
|
T340 |
1 |
| others[1] |
739 |
1 |
|
T123 |
1 |
|
T6 |
3 |
|
T22 |
13 |
| others[2] |
800 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| others[3] |
1358 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T120 |
1 |
| false |
394 |
1 |
|
T204 |
1 |
|
T307 |
1 |
|
T335 |
1 |
| true |
523 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2353 |
1 |
|
T120 |
1 |
|
T111 |
1 |
|
T337 |
1 |
| others[1] |
2301 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T203 |
1 |
| others[2] |
2300 |
1 |
|
T48 |
1 |
|
T131 |
1 |
|
T114 |
1 |
| others[3] |
3786 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T129 |
1 |
| false |
1137 |
1 |
|
T128 |
1 |
|
T204 |
1 |
|
T123 |
1 |
| true |
1558 |
1 |
|
T3 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9083 |
1 |
|
T129 |
1 |
|
T254 |
1 |
|
T306 |
1 |
| others[1] |
295 |
1 |
|
T48 |
1 |
|
T113 |
1 |
|
T127 |
1 |
| others[2] |
260 |
1 |
|
T308 |
1 |
|
T248 |
1 |
|
T342 |
1 |
| others[3] |
440 |
1 |
|
T307 |
1 |
|
T339 |
1 |
|
T8 |
1 |
| false |
152 |
1 |
|
T6 |
4 |
|
T22 |
6 |
|
T25 |
1 |
| true |
3205 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9306 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| others[1] |
452 |
1 |
|
T131 |
1 |
|
T113 |
1 |
|
T307 |
1 |
| others[2] |
472 |
1 |
|
T2 |
1 |
|
T8 |
1 |
|
T6 |
1 |
| others[3] |
793 |
1 |
|
T49 |
1 |
|
T111 |
1 |
|
T254 |
1 |
| false |
234 |
1 |
|
T248 |
1 |
|
T344 |
1 |
|
T19 |
1 |
| true |
2178 |
1 |
|
T48 |
1 |
|
T128 |
1 |
|
T203 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9133 |
1 |
|
T48 |
1 |
|
T131 |
1 |
|
T308 |
1 |
| others[1] |
249 |
1 |
|
T204 |
1 |
|
T332 |
1 |
|
T341 |
1 |
| others[2] |
280 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T128 |
1 |
| others[3] |
407 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| false |
129 |
1 |
|
T254 |
1 |
|
T19 |
2 |
|
T22 |
7 |
| true |
3237 |
1 |
|
T111 |
1 |
|
T129 |
1 |
|
T203 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9086 |
1 |
|
T128 |
1 |
|
T306 |
1 |
|
T126 |
1 |
| others[1] |
229 |
1 |
|
T336 |
1 |
|
T28 |
3 |
|
T22 |
8 |
| others[2] |
290 |
1 |
|
T48 |
1 |
|
T129 |
1 |
|
T254 |
1 |
| others[3] |
405 |
1 |
|
T131 |
1 |
|
T113 |
1 |
|
T340 |
1 |
| false |
148 |
1 |
|
T248 |
1 |
|
T8 |
1 |
|
T22 |
4 |
| true |
3277 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9644 |
1 |
|
T50 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| others[1] |
799 |
1 |
|
T46 |
1 |
|
T129 |
1 |
|
T203 |
1 |
| others[2] |
788 |
1 |
|
T113 |
1 |
|
T308 |
1 |
|
T332 |
1 |
| others[3] |
1293 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T119 |
1 |
| false |
402 |
1 |
|
T307 |
1 |
|
T3 |
1 |
|
T6 |
2 |
| true |
509 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T19 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9594 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T131 |
1 |
| others[1] |
793 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T128 |
1 |
| others[2] |
777 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T339 |
1 |
| others[3] |
1273 |
1 |
|
T114 |
1 |
|
T117 |
1 |
|
T337 |
1 |
| false |
451 |
1 |
|
T119 |
1 |
|
T204 |
1 |
|
T123 |
1 |
| true |
547 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2304 |
1 |
|
T48 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| others[1] |
2247 |
1 |
|
T308 |
1 |
|
T306 |
1 |
|
T335 |
1 |
| others[2] |
2281 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T120 |
1 |
| others[3] |
3855 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T128 |
1 |
| false |
1195 |
1 |
|
T338 |
1 |
|
T22 |
8 |
|
T26 |
2 |
| true |
1553 |
1 |
|
T3 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9102 |
1 |
|
T46 |
1 |
|
T129 |
1 |
|
T203 |
1 |
| others[1] |
284 |
1 |
|
T49 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[2] |
290 |
1 |
|
T111 |
1 |
|
T254 |
1 |
|
T6 |
4 |
| others[3] |
458 |
1 |
|
T50 |
1 |
|
T308 |
1 |
|
T335 |
1 |
| false |
139 |
1 |
|
T131 |
1 |
|
T114 |
1 |
|
T332 |
1 |
| true |
3162 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T120 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |