Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9327 |
1 |
|
T50 |
1 |
|
T113 |
1 |
|
T254 |
1 |
| others[1] |
457 |
1 |
|
T48 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| others[2] |
427 |
1 |
|
T46 |
1 |
|
T19 |
3 |
|
T28 |
1 |
| others[3] |
777 |
1 |
|
T49 |
1 |
|
T129 |
1 |
|
T308 |
1 |
| false |
220 |
1 |
|
T334 |
1 |
|
T2 |
1 |
|
T22 |
3 |
| true |
2227 |
1 |
|
T119 |
1 |
|
T120 |
1 |
|
T131 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9090 |
1 |
|
T337 |
1 |
|
T344 |
1 |
|
T1 |
1 |
| others[1] |
248 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T203 |
1 |
| others[2] |
269 |
1 |
|
T114 |
1 |
|
T204 |
1 |
|
T341 |
1 |
| others[3] |
440 |
1 |
|
T131 |
1 |
|
T117 |
1 |
|
T307 |
1 |
| false |
134 |
1 |
|
T113 |
1 |
|
T254 |
1 |
|
T2 |
1 |
| true |
3254 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9075 |
1 |
|
T2 |
1 |
|
T22 |
6 |
|
T25 |
1 |
| others[1] |
240 |
1 |
|
T120 |
1 |
|
T131 |
1 |
|
T203 |
1 |
| others[2] |
238 |
1 |
|
T48 |
1 |
|
T22 |
15 |
|
T56 |
11 |
| others[3] |
408 |
1 |
|
T49 |
1 |
|
T335 |
1 |
|
T248 |
1 |
| false |
133 |
1 |
|
T114 |
1 |
|
T337 |
1 |
|
T306 |
1 |
| true |
3341 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9591 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T120 |
1 |
| others[1] |
796 |
1 |
|
T128 |
1 |
|
T308 |
1 |
|
T123 |
1 |
| others[2] |
803 |
1 |
|
T204 |
1 |
|
T334 |
1 |
|
T306 |
1 |
| others[3] |
1311 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T131 |
1 |
| false |
426 |
1 |
|
T49 |
1 |
|
T254 |
1 |
|
T337 |
1 |
| true |
508 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9632 |
1 |
|
T119 |
1 |
|
T111 |
1 |
|
T129 |
1 |
| others[1] |
786 |
1 |
|
T50 |
1 |
|
T131 |
1 |
|
T254 |
1 |
| others[2] |
753 |
1 |
|
T120 |
1 |
|
T114 |
1 |
|
T117 |
1 |
| others[3] |
1288 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T128 |
1 |
| false |
458 |
1 |
|
T49 |
1 |
|
T339 |
1 |
|
T341 |
1 |
| true |
518 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2303 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T119 |
1 |
| others[1] |
2259 |
1 |
|
T128 |
1 |
|
T129 |
1 |
|
T113 |
1 |
| others[2] |
2346 |
1 |
|
T46 |
1 |
|
T203 |
1 |
|
T117 |
1 |
| others[3] |
3799 |
1 |
|
T50 |
1 |
|
T114 |
1 |
|
T204 |
1 |
| false |
1156 |
1 |
|
T120 |
1 |
|
T131 |
1 |
|
T340 |
1 |
| true |
1572 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9084 |
1 |
|
T46 |
1 |
|
T114 |
1 |
|
T306 |
1 |
| others[1] |
265 |
1 |
|
T308 |
1 |
|
T337 |
1 |
|
T334 |
1 |
| others[2] |
278 |
1 |
|
T119 |
1 |
|
T120 |
1 |
|
T127 |
1 |
| others[3] |
466 |
1 |
|
T128 |
1 |
|
T113 |
1 |
|
T254 |
1 |
| false |
135 |
1 |
|
T6 |
2 |
|
T22 |
3 |
|
T56 |
2 |
| true |
3207 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9280 |
1 |
|
T50 |
1 |
|
T332 |
1 |
|
T2 |
2 |
| others[1] |
485 |
1 |
|
T119 |
1 |
|
T334 |
1 |
|
T306 |
1 |
| others[2] |
447 |
1 |
|
T120 |
1 |
|
T341 |
1 |
|
T19 |
1 |
| others[3] |
740 |
1 |
|
T128 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| false |
238 |
1 |
|
T248 |
1 |
|
T6 |
1 |
|
T22 |
6 |
| true |
2245 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9103 |
1 |
|
T254 |
1 |
|
T127 |
1 |
|
T22 |
8 |
| others[1] |
267 |
1 |
|
T111 |
1 |
|
T3 |
1 |
|
T22 |
13 |
| others[2] |
278 |
1 |
|
T46 |
1 |
|
T307 |
1 |
|
T339 |
1 |
| others[3] |
440 |
1 |
|
T203 |
1 |
|
T113 |
1 |
|
T117 |
1 |
| false |
148 |
1 |
|
T48 |
1 |
|
T120 |
1 |
|
T344 |
1 |
| true |
3199 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T119 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9089 |
1 |
|
T204 |
1 |
|
T335 |
1 |
|
T336 |
1 |
| others[1] |
254 |
1 |
|
T120 |
1 |
|
T203 |
1 |
|
T337 |
1 |
| others[2] |
258 |
1 |
|
T131 |
1 |
|
T123 |
1 |
|
T338 |
1 |
| others[3] |
402 |
1 |
|
T49 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| false |
154 |
1 |
|
T306 |
1 |
|
T3 |
1 |
|
T20 |
1 |
| true |
3278 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9636 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T128 |
1 |
| others[1] |
794 |
1 |
|
T117 |
1 |
|
T306 |
1 |
|
T6 |
3 |
| others[2] |
744 |
1 |
|
T111 |
1 |
|
T131 |
1 |
|
T114 |
1 |
| others[3] |
1331 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T50 |
1 |
| false |
422 |
1 |
|
T129 |
1 |
|
T336 |
1 |
|
T338 |
1 |
| true |
508 |
1 |
|
T1 |
1 |
|
T19 |
6 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9629 |
1 |
|
T49 |
1 |
|
T129 |
1 |
|
T203 |
1 |
| others[1] |
799 |
1 |
|
T128 |
1 |
|
T114 |
1 |
|
T254 |
1 |
| others[2] |
769 |
1 |
|
T50 |
1 |
|
T307 |
1 |
|
T6 |
8 |
| others[3] |
1310 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T119 |
1 |
| false |
406 |
1 |
|
T336 |
1 |
|
T341 |
1 |
|
T248 |
1 |
| true |
522 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2252 |
1 |
|
T50 |
1 |
|
T344 |
1 |
|
T126 |
1 |
| others[1] |
2270 |
1 |
|
T204 |
1 |
|
T337 |
1 |
|
T335 |
1 |
| others[2] |
2321 |
1 |
|
T120 |
1 |
|
T113 |
1 |
|
T117 |
1 |
| others[3] |
3813 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T49 |
1 |
| false |
1227 |
1 |
|
T119 |
1 |
|
T203 |
1 |
|
T114 |
1 |
| true |
1552 |
1 |
|
T19 |
6 |
|
T20 |
1 |
|
T6 |
16 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9072 |
1 |
|
T111 |
1 |
|
T204 |
1 |
|
T337 |
1 |
| others[1] |
262 |
1 |
|
T120 |
1 |
|
T117 |
1 |
|
T338 |
1 |
| others[2] |
261 |
1 |
|
T129 |
1 |
|
T126 |
1 |
|
T2 |
1 |
| others[3] |
424 |
1 |
|
T128 |
1 |
|
T113 |
1 |
|
T114 |
1 |
| false |
139 |
1 |
|
T49 |
1 |
|
T308 |
1 |
|
T336 |
1 |
| true |
3277 |
1 |
|
T46 |
1 |
|
T48 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9302 |
1 |
|
T46 |
1 |
|
T337 |
1 |
|
T123 |
1 |
| others[1] |
445 |
1 |
|
T48 |
1 |
|
T131 |
1 |
|
T203 |
1 |
| others[2] |
470 |
1 |
|
T120 |
1 |
|
T111 |
1 |
|
T332 |
1 |
| others[3] |
766 |
1 |
|
T119 |
1 |
|
T113 |
1 |
|
T307 |
1 |
| false |
248 |
1 |
|
T117 |
1 |
|
T19 |
2 |
|
T22 |
5 |
| true |
2204 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T128 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9112 |
1 |
|
T254 |
1 |
|
T332 |
1 |
|
T339 |
1 |
| others[1] |
289 |
1 |
|
T49 |
1 |
|
T119 |
1 |
|
T131 |
1 |
| others[2] |
241 |
1 |
|
T203 |
1 |
|
T113 |
1 |
|
T22 |
6 |
| others[3] |
459 |
1 |
|
T120 |
1 |
|
T111 |
1 |
|
T204 |
1 |
| false |
105 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T129 |
1 |
| true |
3229 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T114 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9057 |
1 |
|
T120 |
1 |
|
T113 |
1 |
|
T334 |
1 |
| others[1] |
272 |
1 |
|
T50 |
1 |
|
T117 |
1 |
|
T337 |
1 |
| others[2] |
256 |
1 |
|
T119 |
1 |
|
T332 |
1 |
|
T340 |
1 |
| others[3] |
459 |
1 |
|
T111 |
1 |
|
T204 |
1 |
|
T336 |
1 |
| false |
140 |
1 |
|
T48 |
1 |
|
T338 |
1 |
|
T22 |
7 |
| true |
3251 |
1 |
|
T46 |
1 |
|
T49 |
1 |
|
T128 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9649 |
1 |
|
T50 |
1 |
|
T120 |
1 |
|
T128 |
1 |
| others[1] |
796 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T129 |
1 |
| others[2] |
779 |
1 |
|
T46 |
1 |
|
T111 |
1 |
|
T203 |
1 |
| others[3] |
1311 |
1 |
|
T49 |
1 |
|
T131 |
1 |
|
T113 |
1 |
| false |
390 |
1 |
|
T332 |
1 |
|
T336 |
1 |
|
T248 |
1 |
| true |
510 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9578 |
1 |
|
T128 |
1 |
|
T129 |
1 |
|
T337 |
1 |
| others[1] |
769 |
1 |
|
T48 |
1 |
|
T203 |
1 |
|
T308 |
1 |
| others[2] |
800 |
1 |
|
T49 |
1 |
|
T50 |
1 |
|
T120 |
1 |
| others[3] |
1358 |
1 |
|
T46 |
1 |
|
T119 |
1 |
|
T131 |
1 |
| false |
410 |
1 |
|
T111 |
1 |
|
T123 |
1 |
|
T344 |
1 |
| true |
520 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2358 |
1 |
|
T50 |
1 |
|
T119 |
1 |
|
T308 |
1 |
| others[1] |
2287 |
1 |
|
T111 |
1 |
|
T131 |
1 |
|
T114 |
1 |
| others[2] |
2254 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T254 |
1 |
| others[3] |
3820 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T120 |
1 |
| false |
1197 |
1 |
|
T113 |
1 |
|
T337 |
1 |
|
T341 |
1 |
| true |
1519 |
1 |
|
T19 |
6 |
|
T20 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9107 |
1 |
|
T340 |
1 |
|
T8 |
1 |
|
T6 |
2 |
| others[1] |
293 |
1 |
|
T49 |
1 |
|
T307 |
1 |
|
T306 |
1 |
| others[2] |
263 |
1 |
|
T50 |
1 |
|
T254 |
1 |
|
T28 |
1 |
| others[3] |
437 |
1 |
|
T46 |
1 |
|
T131 |
1 |
|
T337 |
1 |
| false |
134 |
1 |
|
T129 |
1 |
|
T248 |
1 |
|
T1 |
1 |
| true |
3201 |
1 |
|
T48 |
1 |
|
T119 |
1 |
|
T120 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9310 |
1 |
|
T203 |
1 |
|
T113 |
1 |
|
T19 |
2 |
| others[1] |
423 |
1 |
|
T340 |
1 |
|
T341 |
1 |
|
T6 |
1 |
| others[2] |
473 |
1 |
|
T128 |
1 |
|
T129 |
1 |
|
T339 |
1 |
| others[3] |
750 |
1 |
|
T46 |
1 |
|
T307 |
1 |
|
T335 |
1 |
| false |
249 |
1 |
|
T117 |
1 |
|
T336 |
1 |
|
T2 |
1 |
| true |
2230 |
1 |
|
T48 |
1 |
|
T49 |
1 |
|
T50 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9056 |
1 |
|
T120 |
1 |
|
T308 |
1 |
|
T28 |
1 |
| others[1] |
274 |
1 |
|
T48 |
1 |
|
T50 |
1 |
|
T111 |
1 |
| others[2] |
260 |
1 |
|
T119 |
1 |
|
T22 |
11 |
|
T25 |
1 |
| others[3] |
460 |
1 |
|
T49 |
1 |
|
T129 |
1 |
|
T114 |
1 |
| false |
151 |
1 |
|
T341 |
1 |
|
T8 |
1 |
|
T22 |
4 |
| true |
3234 |
1 |
|
T46 |
1 |
|
T128 |
1 |
|
T131 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9066 |
1 |
|
T120 |
1 |
|
T254 |
1 |
|
T22 |
12 |
| others[1] |
256 |
1 |
|
T48 |
1 |
|
T248 |
1 |
|
T126 |
1 |
| others[2] |
254 |
1 |
|
T128 |
1 |
|
T204 |
1 |
|
T337 |
1 |
| others[3] |
421 |
1 |
|
T49 |
1 |
|
T114 |
1 |
|
T117 |
1 |
| false |
145 |
1 |
|
T131 |
1 |
|
T2 |
1 |
|
T22 |
5 |
| true |
3293 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9610 |
1 |
|
T46 |
1 |
|
T50 |
1 |
|
T119 |
1 |
| others[1] |
784 |
1 |
|
T120 |
1 |
|
T129 |
1 |
|
T113 |
1 |
| others[2] |
831 |
1 |
|
T254 |
1 |
|
T308 |
1 |
|
T6 |
4 |
| others[3] |
1292 |
1 |
|
T48 |
1 |
|
T111 |
1 |
|
T128 |
1 |
| false |
413 |
1 |
|
T49 |
1 |
|
T117 |
1 |
|
T337 |
1 |
| true |
505 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |